View MT29F8G08ABCBB_1641459.PDF datasheet online --- IC-ON-LINE

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?products and specifications discussed here in are for evaluation and re ference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. draft 2/ 27/ 2009 8gb asynchronous/synchronous nand flash memory features micron confidential and proprietary advance ? pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. 1.0 2/09 en 1 ?2008 micron technology, inc. all rights reserved. nand flash memory mt29f8g08ababa, MT29F8G08ABCBB features ? open nand flash interface (onfi) 2.0-compliant 1 ? single-level cell (slc) technology ? organization ? page size x8: 4,320 bytes (4,096 + 224 bytes) ? block size: 128 pages (512k + 28k bytes) ? plane size: 2 planes x 1,024 blocks per plane ? device size: 8gb: 2,048 blocks ? synchronous i/o performance ? clock rate: 12ns (ddr) ? read/write throughput per pin: 166 mt/s ? asynchronous i/o performance ? t rc/ t wc: 25ns (min) ? array performance ? read page: 25s (max) ? program page: 200s (typ) ? erase block: 700s (typ) ? operating voltage range ? vcc: 2.7?3.6v ? vccq: 1.7?1.95v, 2.7?3.6v ? command set: onfi nand flash protocol ? advanced command set ? program cache ? read cache sequential ? read cache random ? one-time programmable (otp) mode ? multi-plane commands ? multi-lun operations ? read unique id ? copyback ? first block (block address 00h) is valid with ecc 2 ? reset (ffh) required as first command after power-on ? operation status byte provides software method for detecting ? operation completion ? pass/fail condition ? write-protect status ? data strobe (dqs) signals provide a hardware method for synchronizing data i/o in the synchronous interface ? copyback operations supported within the plane from which data is read ? quality and reliability ? data retention: 10 years ? endurance: 100,000 program/erase cycles 2 ? operating temperature: ? commercial: 0c to +70c ? industrial: ?40c to +85c ?package ? 48-pin tsop ? 52-pad lga ? 100-ball bga notes: 1. the onfi 2.0 specification is available at www.onfi.org. 2. for further details, see ?error management? on page 95.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. 1.0 2/09 en 2 ?2008 micron technology, inc. all rights reserved. 8gb asynchronous/synchronous nand flash memory part numbering information micron confidential and proprietary advance part numbering information micron nand flash devices are available in different config urations and densities (see figure 1). figure 1: marketing part number chart notes: 1. lead-free package. valid part number combinations after building the part number from the part numbering chart, verify that the part is offered and valid by using the micron parametric part search web site at: www.micron.com/products/parametric. if the device required is not on this list, contact the factory. mt 29f 8g 08 a b a b a wp es :b micron technology single-supply nand flash 29f = single-supply nand flash memory density 8g = 8gb device width 08 = 8 bits level bit/cell a 1-bit classification die # of ce# # of r/b# i/o b 1 1 1 common operating voltage range a = vcc: 3.3v (2.7C3.6v), vccq: 3.3v (2.7C3.6v) c = vcc: 3.3v (2.7C3.6v), vccq: 1.8v (1.7C1.95v) generation feature set b = second set of device features interface a = async only b = sync / async design revision b = second revision production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample reserved for future use blank operating temperature range blank = commercial (0c to +70c) it = industrial (C40c to +85c) speed grade (synchronous mode only) 12 = 166 mt/s package code c3 = 52-pad ulga 12mm x 17mm x 0.65mm 1 h1 = 100-ball vbga 12mm x 18mm x 1.0mm 1 wp = 48-pin tsop 1 (cpl) wc = 48-pin tsop 1 (ocpl)
draft 2/ 27/ 2009 pdf: 09005aef8386131b/source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. 1.0 2/09 en 3 ?2008 micron technology, inc. all rights reserved. 8gb asynchronous/synchronous nand flash memory table of contents micron confidential and proprietary advance table of contents part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 addressing and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 device and array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 asynchronous interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 asynchronous enable/standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 asynchronous bus idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 asynchronous commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 asynchronous addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 asynchronous data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 asynchronous data output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 write protect (wp#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 ready/busy# (r/b#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 synchronous interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 synchronous enable/standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 synchronous bus idle/driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 synchronous commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 synchronous addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 synchronous ddr data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 synchronous ddr data output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 write protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 vcc power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 activating interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 activating the asynchronous interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 activating the synchronous interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 reset operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 reset (ffh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 synchronous reset (fch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 identification operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 read id (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 read parameter page (ech) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 read unique id (edh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 configuration operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 set features efh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 get features (eeh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 status operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 read status (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 select lun with status (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 column address operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 change read column (05h-e0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 select cache register (06h-e0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 change write column (85h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 change row address (85h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 read mode (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 read page (00h?30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 read page cache sequential (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
draft 2/ 27/ 2009 pdf: 09005aef8386131b/source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. 1.0 2/09 en 4 ?2008 micron technology, inc. all rights reserved. 8gb asynchronous/synchronous nand flash memory table of contents micron confidential and proprietary advance read page cache random (00h?31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 read page cache last (3fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 page read multi-plane (00h-32h) using cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 read page multi-plane (00h?32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 program page operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 program page cache operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 program page multi-plane program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 program page multi-plane program cache operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 program page (80h?10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 program page cache (80h?15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 program page multi-plane 80h-11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 multi-plane erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 erase block (60h?d0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 erase block multi-plane (60h?d1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 copyback operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 copyback read (00h?35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 copyback program (85h?10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 copyback read multi-plane (00h-32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 copyback program multi-plane (85h-11h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 one-time programmable (otp) operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 program otp page (80h?10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 protect otp area (80h?10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 read otp page (00h?30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 multi-plane operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 multi-plane addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 multi-lun operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 output drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 synchronous ac overshoot/undershoot specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 synchronous input slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 synchronous output slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 synchronous interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 asynchronous interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
draft 2/ 27/ 2009 pdf: 09005aef8386131b/source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. 1.0 2/09 en 5 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory list of figures micron confidential and proprietary advance list of figures figure 1: marketing part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 2: pin assignment (top view) 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 3: pad assignment (top view) 52-pad lga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: ball assignment ? 100-ball vbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: nand flash lun functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: device organization for single-die package (tsop/bga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7: device organization for single-die package (lga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: asynchronous command latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 10: asynchronous address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 11: asynchronous data input cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 12: asynchronous data output cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 13: asynchronous data output cycles (edo mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: read/busy# open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15: t fall and t rise (v cc q = 3.3v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 16: t fall and t rise (v cc q = 1.8v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17: iol vs. rp (v cc q = 3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: i ol vs. rp (1.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: tc vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 20: synchronous bus idle/d riving behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 21: synchronous command cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 22: synchronous address cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 23: synchronous ddr data input cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 24: synchronous ddr data output cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 25: power cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 26: r/b# power-on behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 27: activating the synchronous interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: asynchronous reset (ffh) cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 29: synchronous reset (fch) cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 30: read id (90h) with 00h address cycle operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 31: read id (90h) with 20h address cycle operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 32: read parameter page (ech) operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 33: read unique id (edh) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 34: set features (efh) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 35: get features (eeh) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 36: read status (70h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 37: select lun with status (78h) op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 38: change read column (05h?e0h) op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 39: select cache register (06h?e0h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 40: change write column (85h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 41: read page (00h?30h) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 42: read page cache sequential (31h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 43: read page cache random (00h?31h ) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 44: read page cache last (3fh) oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 45: read page multi-plane (00h?32h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 46: program page (80h?10h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 47: program page cache (80h?15h) op eration (start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 48: program page cache (80h?15h) op eration (end) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 49: program page multi-plane (80h?11h) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 50: erase block (60h?d0h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 51: erase block multi-plane (60h?d1h ) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 52: copyback read (00h?35h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 53: copyback read (00h?35h) with change read column (05h?e0h) operation . . . . . . . . . . . . .79 figure 54: copyback program (85h?10h) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 55: copyback program (85h?10h) with change wr ite column (85h) operation . . . . . . . . . . . .80 figure 56: copyback program multi-plane (85h?11h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 57: program otp page (80h?10h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
draft 2/ 27/ 2009 pdf: 09005aef8386131b/source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. 1.0 2/09 en 6 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory list of figures micron confidential and proprietary advance figure 58: program otp page (80h?10h ) with change write column (85h) operation . . . . . . . . . . . . .84 figure 59: protect otp area (80h?10h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 60: read otp page (00h?30h) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 61: overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 62: undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 63: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 64: get features operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 65: read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 66: select lun with status operatio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 67: read parameter page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 68: read page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 69: change read column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 70: read page cache sequential (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 71: read page cache sequential (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 72: read page cache random (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 73: read page cache random (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 74: multi-plane read page (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 75: multi-plane read page (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 76: program page operation (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 77: program page operation (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 78: change write column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 79: multi-plane program page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 80: erase block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 81: copyback (1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 82: copyback (2 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 83: copyback (3 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 84: read otp page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 85: program otp page (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 86: program otp page (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 87: protect otp area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 88: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 89: read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 90: select lun with status cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 91: read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 92: read page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 93: read page operation with ce# ?d on?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 94: change read column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 95: read page cache sequential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 96: read page cache random . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 97: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 98: program page op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 99: program page op eration with ce# ?don?t care?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 100: program page operation with ch ange write column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 101: program page cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 102: program page cache ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 103: copyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 104: erase block operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 105: 48-pin tsop type 1 cpl (wp package code). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 106: 48-pin tsop type 1 ocpl (wc pa ckage code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 107: 52-pad ulga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 108: 100-ball vbga (package code h1), 1218. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
draft 2/ 27/ 2009 pdf: 09005aef8386131b/source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_ascyn_sync_nand.fm - rev. 1.0 2/09 en 7 ?2008 micron technology, inc. all rights reserved. 8gb asynchronous/synchronous nand flash memory list of tables micron confidential and proprietary advance list of tables table 1: signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 2: array addressing for 8gb logical unit (lun) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 3: asynchronous interface mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 4: synchronous interface mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 5: command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 6: read id parameters for address 00h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 7: read id parameters for address 20h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 8: parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 9: feature address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 10: feature address 01h: timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 11: feature addresses 10h and 80h: programmable output driv e strength . . . . . . . . . . . . . . . . . . . . . . . .54 table 12: feature addresses 81h: programmable r/b# pull-down stre ngth . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5 table 13: feature addresses 90h: array operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 14: status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 15: error management details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 16: output drive strength test conditions (v cc q = 1.7?1.95v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 17: output drive strength impedance values (vccq = 1.7?1.95v ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 18: output drive strength conditions (vccq = 2.7-3.6v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 19: output drive strength impedance va lues (vccq = 2.7-3.6v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 20: pull-up and pull-down output impedance mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 21: overshoot / undershoot parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 22: test conditions for input slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 23: input slew rate (vccq = 1.7?1.95v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 24: test conditions for output slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 25: output slew rate (vccq = 1.7?1.95v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 26: absolute maximum ratings by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 27: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 28: asynchronous device dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 29: synchronous device dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 30: ball capacitance: bga-100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 31: pin capacitance: tsop-48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 32: pad capacitance: lga-52 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 33: test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 34: 3.3v vccq device operating characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 table 35: 1.8v vccq device operating characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 36: ac characteristic: synchronous comma nd, address, and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table 37: ac characteristics: asynchronous command, address, and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 9 table 38: valid blocks per lun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 39: array characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 8 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory general description micron confidential and proprietary advance general description micron nand flash technology provides hi gh-performance nand flash memory with an interface that supports up to 166 mt/s data read and write throughput. micron nand flash devices include two data interfaces?a synchronous interface for high-performance i/o operations, and an asynchronous interface for legacy nand flash applications. these devi ces use a highly multiplexed 8-bit bus (i/o[7:0], dq[7:0]) to transfer commands, addresses, and data. data transfers in the synchronous interface include a bidirectional data strobe (dqs). between the synchronous and asynchronous interfaces there are five control signals used to implement the nand flash protocol. in the synchronous interface these signals are ce#, cle, ale, clk, and w/r#; in the asyn- chronous interface these signals are ce#, cl e, ale, we#, and re#. additional signals control hardware write protection (wp#) and monitor device status (r/b#). this hardware interface creates a low pin-co unt device with a standard pinout that remains the same from one de nsity to another, enabling future upgrades to higher densities with no board redesign. a logical unit (lun), or die, is the minimum unit that can independently execute commands and report status. there is at le ast one lun per ce#. each lun contains 2 planes. each plane consists of 1,024 blocks. each block is subdivided into 128 program- mable pages. the contents of each page can be programmed in t prog, and an entire block can be erased in t bers. program/erase endurance is specified at 100,000 when using appro- priate error correction code (ecc). these nand devices are onfi 2.0-compliant. the onfi 2.0 specification can be found at www.onfi.org .
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 9 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory general description micron confidential and proprietary advance figure 2: pin assignment (top view) 48-pin tsop type 1 notes: 1. ce2# and r/b2# on are not available and are treated as nc. 2. for asynchronous de vices with vccq = 3. 3v, these signals can be treated as dnu. 3. for synchronous devices with vccq = 1.8v, thes e signals must be supp lied with a 1.8v volt - age supply. 4. signal names in parentheses are the signal na mes when the synchronous interface is active. nc nc nc nc nc r/b2# 1 r/b# re# (w/r#) 4 ce# ce2# 1 nc vcc vss nc nc cle ale we# (clk) 4 wp# nc nc nc nc nc dnu/vssq 2 nc nc nc i/o7 (dq7) 4 i/o6 (dq6) 4 i/o5 (dq5) 4 i/o4 (dq4) 4 nc dnu/vccq 2, 3 dnu vcc vss nc (dqs) 4 dnu/vccq 2, 3 nc i/o3 (dq3) 4 i/o2 (dq2) 4 i/o1 (dq1) 4 i/o0 (dq0) 4 nc nc dnu dnu/vssq 1 z 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 10 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory general description micron confidential and proprietary advance figure 3: pad assignment (top view) 52-pad lga notes: 1. these pads are currently nc and are shown for future placement 2. these pads are currently nc an d are shown for future placement nc dnu dnu/ v ss nc nc nc dnu dnu dnu/ v ss nc ale-1 we#-2 1 i/o0-2 1 i/o1-2 1 i/o2-2 1 dnu/ v cc a b c d e f g h j k l m n v ss ale-2 1 wp#-1 i/o1-1 i/o3-1 v ss cle-1 cle-2 1 we#-1 i/o0-1 i/o2-1 v ss i/o3-2 1 ce# ce2# 1 r/b# wp#-2 1 i/o6-1 i/o4-1 i/o4-2 1 v cc re#-2 1 v ss i/o7-1 i/o5-1 v cc re#-1 r/b2# 1 i/o7-2 1 i/o6-2 1 i/o5-2 1 dnu/ v cc top view, pads down 0 1 2 3 4 5 6 7 8 oa ob oc od oe of r/b4# 2 2 ce4# 2 r/b3# 2 ce3# 2 nc
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 11 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory general description micron confidential and proprietary advance figure 4: ball assignment ? 100-ball vbga notes: 1. n/a: this signal is tri-stated wh en the asynchronous interface is active. 2. signal names in parentheses are the signal na mes when the synchronous interface is active. 3. these pads are currently nc an d are shown for future placement. a b d e f g h j k l m n p t u a b d e f g h j k l m n p t u 2 nc rfu rfu v cc v ss v ss q dq0-2 3 dq0-1 v cc q dq1-2 3 dq1-1 v ss q nc 3 dnu dnu v cc v ss v cc q dq2-2 3 dq2-1 v ss q dq3-2 3 dq3-1 v cc q 4 nc nc v cc v ss rfu ale-2 3 ale-1 v cc q v ss q rfu rfu 5 wp#-2 3 wp#-1 v cc v ss rfu nc nc cle-2 3 cle-1 n/a 1 n/a 1 6 nc nc v cc v ss r/b2# 3 r/b# ce2# 3 re#-2 3 re#-1 rfu rfu 7 nc nc v cc v ss nc nc ce# v cc q v ss q we#-2 3 we#-1 8 dnu dnu v cc v ss v cc q dq5-2 3 dq5-1 v ss q dq4-2 3 dq4-1 v cc q 9 nc rfu rfu v cc v ss v ss q dq7-2 3 dq7-1 v cc q dq6-2 3 dq6-1 v ss q nc 1 nc nc nc nc 10 nc nc nc nc (w/r#-1) (w/r#-2) (clk-1) (clk-2) (dqs-1) ball-down top view 1 2 3 4 5 6 7 8 9 10 (dqs-2 3 )
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 12 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory general description micron confidential and proprietary advance notes: 1. see ?device and array organization? on page 14 for detailed signal connections. 2. see ?bus operation? on page 16 for detailed asynchronous and synchronous interface sig - nal-use explanations. 3. these signals are currently nc an d are shown for future placement. table 1: signal definitions symbol 1 type description 2 async sync ale, ale-1, (ale-2) 3 ale, ale-1, (ale-2) 3 input address latch enable: loads an address from i/o[7:0], dq[7:0] into the address register. ce#, (ce2#,ce3#,ce4#) 3 ce#, (ce2#) 3 input chip enable: a signal that enables or disa bles one or more luns in a target 1 . cle, cle-1, (cle-2) 3 cle, cle-1, (cle-2) 3 input command latch enable: loads a command from i/o[7:0], dq[7:0] into the command register. i/o[7:0], i/o[7:0]-1, dq[7:0] dq[7:0]-1 (i/o[7:0]-2) 3 (dq[7:0]-2) 3 dq[7:0], dq[7:0]-1, (i/o[7:0]-2) 3 (dq[7:0]-2) 3 i/o data inputs/outputs: the bidirectional i/os transfer address, data, and command information. n/a dqs, dqs-1, dqs-2 i/o data strobe: provides a synchronous re ference for data input and output. re#, re#-1, (re#-2) 3 w/r#, w/r#-1, (w/r#-2) 3 input read enable and write/read: re# transfers serial data from the nand flash to the host system when the asynchronous interface is active. when the synchronous interface is ac tive, w/r# controls the direction of dq[7:0] and dqs. we#, we#-1, (we#-2) 3 clk, clk-1, (cle-2) 3 input write enable and clock: we# transfers commands, addresses, and serial data from the host syste m to the nand flash when the asynchronous interface is active. when the synchronous interface is active, clk latches comm and and address cycles. wp#, wp#-1, (wp#-2) 3 wp#, wp#-1, (wp#-2) 3 input write protect: wp# is a signal that enables or disables array program and erase operations. r/b#, (r/b2#,r/b3#,r/b4#) 3 r/b#, (r/b2#,r/b3#,r/b4#) 3 output ready/busy: an open-drain, active-low output that requires an external pull-up resistor. this signa l indicates target array activity. vcc vcc supply vcc: core power supply vccq vccq supply vccq: i/o power supply vss vss supply vss: core ground connection vssq vssq supply vssq: i/o ground connection nc nc ? no connect: ncs are not internally connected. they can be driven or left unconnected. dnu dnu ? do not use: dnus must be left unconnected. rfu rfu ? reserved for future use: rfus must be left unconnected.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 13 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory architecture micron confidential and proprietary advance architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins and received by i/o control circuits. the commands received at the i/o control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. the addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address. data is transferred to or from the nand flash memory array, byte-by-byte, through a data register and a cache register. see figure 5 for details. the nand flash memory array is programme d and read using page-based operations and is erased using block-based operations. during normal page operations, the data and cache registers act as a single register. during cache operations, the data and cache registers operate independently to increase data throughput. the status register reports th e status of lun operations. figure 5: nand flash lun functional block diagram notes: 1. n/a: this signal is tri-stated wh en the asynchronous interface is active. 2. signal names in parentheses are the signal na mes when the synchronous interface is active. status register command register ce# v ccq v ssq cle n/a (dqs) ale re# (w/r#) wp# i/o[7:0] (dq[7:0]) we# (clk) r/b# v cc v ss control logic data register cache register row decode column decode nand flash array data register cache register row decode column decode nand flash array (2 planes) address register i/o control
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 14 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory addressing and memory map micron confidential and proprietary advance addressing and memory map nand flash devices do not contain dedicate d address pins. addresses are loaded using a 5-cycle sequence shown in table 2 on page 23. device and array organization figure 6: device organization for single-die package (tsop/bga) notes: 1. signal names not in parentheses are for ts op packages. signal names in parentheses are for bga packages. figure 7: device organization for single-die package (lga) ce# cle (cle-1) ale (ale-1) we# (clk) re# (w/r#) i/o[7:0] (dq[7:0]) n/a (dqs) wp# (wp#-1) lun 1 target 1 package r/b# ce# cle-1 ale-1 we#-1 re#-1 i/o[7:0]-1 wp#-1 lun 1 target 1 package r/b#
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 15 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory device and array organization micron confidential and proprietary advance figure 8: array organization for 8gb logical unit (lun) notes: 1. cax = column address, pax = page address, bax = block address, lax = lun address; the page address, block address, and lun address are collectively called the row address. 2. when using the synchronous interface, ca0 is forced to 0 internally; one data cycle always returns one even byte and one odd byte. 3. column addresses 4,320 (10e0h ) through 8,191 (1fffh) are invalid, "out of bounds," do not exist in the device, and cannot by addressed. 4. ba[8] is the plane-select bit: plane 0: ba[7] = "0" plane 1: ba[7] = "1" table 2: array addressing for 8gb logical unit (lun) cycle i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 2 second low low low ca12 3 ca11 ca10 ca9 ca8 third ba7 4 pa6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low ba17 ba16 cache registers data registers 1,024 blocks per plane 2,048 blocks per lun 1 block 1 block plane 0 (0, 2, 4, ..., 2,046) plane 1 (1, 3, 5, ..., 2,047) 224 4,096 224 4,320 bytes 4,320 bytes 224 224 4,096 4,096 4,096 1 block 1 page = (4k + 224 bytes) 1 block = (4k + 224) bytes x 128 pages = (512k + 28k) bytes 1 plane = (512k + 28k) bytes x 1,024 blocks = 4,320mb 1 lun = 4,320mb x 2 planes = 8,640mb dq0 dq7 logical unit (lun)
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 16 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance bus operation these nand flash devices have two interfaces : a synchronous interface for fast data i/o transfer and an asynchronous interface that is backwards compatible with existing nand flash devices. the nand flash command protocol for both the asynchronous and synchronous inter- faces is identical. however, there are some differences between the asynchronous and synchronous interfaces when issuing command, address, and data i/o cycles using the nand flash signals. asynchronous interface the asynchronous interface is active when th e nand flash device powers on to provide compatibility with existing nand controll ers that may not support the synchronous interface. the dqs signal is tri-stated wh en the asynchronous interface is active. asynchronous interface bus modes are summarized in table 3 on page 16. notes: 1. dqs is tri-stated when the asynchronous interface is active. 2. wp# should be biased to cmos low or high for standby. 3. mode selection settings for this table: h = lo gic level high; l = logic level low; x = vih or vil. asynchronous enable/standby a target is disabled when ce# is driven high , even when the target is busy. when ce# is driven low, all of the signals for that target are enabled. with ce# low, the target can accept commands, addresses, and data i/o. there may be more than one target in a nand flash package. each target is controlled by its own ce#; the first target is controlled by ce#; the second target (if present) is controlled by ce2#, etc. a target is disabled when ce# is driven high , even when the target is busy. all of the target's signals are disabled except ce#, wp#, and r/b#. this enables the nand flash to share the same memory bus with other flash or sram devices. while the target is disabled, other devices on the memory bus can be accessed. table 3: asynchronous interface mode selection mode ce# cle ale we# re# dqs 1 i/o[7:0] dq[7:0] wp# 2 standby hxxxxx x0v/vccq 2 bus idle lxxhhx x x command input lhl hx x h address input llh hx x h data input lll hx x h data output lllh x x x write protect xxxxxx x l
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 17 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance a target enters low-power standby when it is di sabled and is not busy. if the target is busy when it is disabled, the target enters standb y after all of the luns complete their opera- tions. standby helps reduce power consumption. asynchronous bus idle a target's bus is idle when ce# is low, we# is high, and re# is high. during bus idle, all of the signals are enabled except dqs, which is not used when the asynchronous interface is active. no commands, addresses, and data are latched into the target; no data is output. asynchronous commands an asynchronous command is written from i/o[7:0], dq[7:0] to the command register on the rising edge of we# when ce# is low, ale is low, cle is high, andre# is high. commands are typically ignored by luns that are busy; however, some commands, including read status (70h) and select lu n with status (78h), are accepted by luns even when they are busy. figure 9: asynchrono us command latch cycle asynchronous addresses an asynchronous address is written from i/o[ 7:0], dq[7:0] to the address register on the rising edge of we# when ce# is low, ale is high, cle is low, and re# is high. bits that are not part of the address space must be low (see table 2 on page 23). the number of cycles required for each command varies. refer to the command descriptions to determine addressing requirements (see ?command definitions? on page 39"). addresses are typically ignored by luns that are busy; however, some addresses are accepted by luns even when they are busy; for example, like address cycles that follow the select lun with status (78h) command. we# ce# ale cle i/ox, dqx command t wp t ch t cs t alh t dh t ds t als t clh t cls dont care
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 18 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 10: asynchronous address latch cycle asynchronous data input data is written from i/o[7:0], dq[7:0] to the cache register of the selected lun on the rising edge of we# when: ?ce# is low, ?ale is low, ?cle is low, and ?re# is high. data input is ignored by luns that are not selected or are busy, except if the lun is busy with a program page cache mode operation. we# ce# ale cle i/ox, dqx col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 row add 3 dont care undefined t wc
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 19 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 11: asynchronous data input cycles asynchronous data output data can be output from a lun if it is in a ready state. data output is supported following a read operation from the nand flash array. data is output from the cache register of the selected lun to i/o[7:0], dq[7:0] on the falling edge of re# when: ?ce# is low, ?ale is low, ?cle is low, and ?we# is high. if the host controller is using a t rc of 30ns or greater, the host can latch the data on the rising edge of re# (see figure 12 on page 20). if the host controller is using a t rc of less than 30ns, the host can latch the data on the next falling edge of re# [see figure 13 on page 20 for extended data output (edo) timing]. using the select lun with status (78h ) command prevents data contention following a multi-lun operation. once a select lun with status (78h) command has been issued to a lun, then issue the read mode (00h) command. data can now be output from the selected lun. data output requests are typically ignored by a lun that is busy; however, it is possible to output data from the status register even when a lun is busy by first issuing the read status or select lun with status (78h) command. we# ce# ale cle i/ox, dqx t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in m+1 d in n dont care t wc d in m
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 20 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 12: asynchronous data output cycles figure 13: asynchronous data output cycles (edo mode) ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea dont care t rhz t chz t rhz t rhoh r/b# t coh d out d out d out d out d out d out ce# re# i/ox, dqx rdy t rr t cea t rea t rp t reh t rc t rloh t rea t rhoh t rhz t coh t chz dont care
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 21 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance write protect (wp#) the wp# signal enables or disables progra m and erase operations to a target. when wp# is low, program and erase operations are disabled. when wp# is high, program and erase operations are enabled. it is recommended that the host drive wp# low during power-on until vcc and vccq are stable to prevent inadvertent program and erase operations (see ?vcc power cycling? on page 35 for additional details). wp# must be transitioned only when the ta rget is not busy and prior to beginning a command sequence. after a command sequence is complete and the target is ready, wp# can be transitioned. after wp# is transitioned the host must wait t ww before issuing a new command. the wp# signal is always an ac tive input, even when ce# is high. this signal should not be multiplexed with other signals. ready/busy# (r/b#) the r/b# signal provides a hardware method of indicating whether a target is ready or busy. a target is busy when one or more of its luns are busy (rdy = "0"). a target is ready when all of its luns are ready (rdy = "1"). because each lun contains a status register, it is possible to determine the independent status of each lun by polling its status register instead of using the r/b# signal (see ?status operations? on page 56 for details regarding lun status). this signal requires a pull-up resistor, rp, for proper operation. r/b# is high when the target is ready, and transitions low when the target is busy. the signal's open-drain driver enables multiple r/b# outputs to be or-tied. typically, r/b# is connected to an interrupt pin on the system controller (see figure 14 on page 22). the combination of rp and capacitive loadin g of the r/b# circuit determines the rise time of the r/b# signal. the actual value used for rp depends on the system timing requirements. large values of rp cause r/b# to be delayed significantly. between the 10- to 90-percent points on the r/b# waveform, the rise time is approximately two time constants (tc). the fall time of the r/b# signal is determin ed mainly by the output impedance of the r/ b# signal and the total load capacitance. approximate rp values using a circuit load of 100pf are provided in figure 19 on page 24. the minimum value for rp is determined by the output drive capability of the r/b# signal, the output voltage swing, and vccq. tc r c = where r rp (resistance of pull-up resisto r), and c total capacitive load. = = rp v cc max () v ol max () ? i ol il + --------------------------------------------------------------- = where il is the sum of the input currents of all devices tied to the r/b# pin.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 22 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 14: read/busy# open drain figure 15: t fall and t rise (v cc q = 3.3v) notes: 1. t fall and t rise calculated at 10 percent.90 percent points. 2. t rise dependent on external capacitance and resistive loading and ou tput transistor imped - ance. 3. t rise primarily dependent on external pull-u p resistor and external capacitive loading. 4. t fall =10ns at 3.3v 5. see tc values in figure 19 on page 24 for approximate rp value and tc. rp v cc v cc q r/b# open drain output i ol v ss device to controller 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 C1 0 2 4 0 2 4 6 t fall t rise vccq 3.3v tc v
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 23 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 16: t fall and t rise (v cc q = 1.8v) notes: 1. t fall and t rise are calculated at 10 percent and 90 percent points. 2. t rise is primarily dependent on external pull -up resistor and extern al capacitive loading. 3. t fall 7ns at 1.8v. 4. see tc values in figure 19 on page 24 for tc and approximate rp value. figure 17: iol vs. rp (v cc q = 3.3v) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise vccq 1.8v tc v 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 4000 6000 8000 10000 12000 iol at 3.60v (max) rp i(ma)
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 24 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 18: i ol vs. rp (1.8v) figure 19: tc vs. rp 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2,000 4,000 6,000 8,000 10,000 12,000 rp ( ) i (ma) i ol at 1.95v (ma) 1200 1000 800 600 400 200 0 0 2k : 4k : 6k : 8k : 10k : 12k : i ol at v cc q (max) rc = tc c = 100pf rp t(ns)
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 25 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance synchronous interface when the synchronous interface is activated on a target (see ?activating the synchro- nous interface? on page 37), the target is capable of high-speed ddr data transfers. existing signals are redefined for high-speed ddr i/o. the we# signal becomes clk. dqs is enabled. the re# signal becomes w/r#. clk provides a clock reference to the nand flash device. dqs is a bidirectional data strobe. during data output, dqs is driven by the nand flash device. during data input, dqs is controlled by the host controller while inputting data on dq[7:0]. the direction of dqs and dq[7:0] is controlled by the w/r# signal. when the w/r# signal is latched high, the controller is dr iving the dq bus and dqs. when the w/r# is latched low, the nand flash is driving the dq bus and dqs. the synchronous interface bus modes are summarized in table 4. notes: 1. clk can be stopped when the target is disabled, even when r/b# is low. 2. wp# should be biased to cmos low or high for standby. 3. commands and addresses are latche d on the rising edge of clk. table 4: synchronous interface mode selection mode ce# cle ale clk 1 w/r# dqs dq[7:0] wp# 2 notes standby hxxxxxx0v/vccq bus idle lll hxx x bus driving l l l l output x x command input lhl hxx h 3 address input llh hxx h 3 data input lhh h x h 4 data output lhh lnote 5x x 5 write protect xxxxxxx l undefined llh lxx x undefined lhl lxx x
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 26 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance 4. during data input to the device, dqs is the ?c lock? that latches the da ta in the cache regis - ter. 5. during data output from the nand flash devi ce, dqs is an output generated from clk after t dqsck delay. 6. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . synchronous enable/standby in addition to the description in the section ?asynchronous enable/standby? on page 16, the following requirements also apply when the synchronous interface is active. before enabling a target, clk must be running and ale and cle must be low. when ce# is driven low, all of the signals for the se lected target are enabled. the target is not enabled until t cs completes; the target's bus is then idle. prior to disabling a target, the target's bus must be idle (see ?synchronous bus idle/ driving? on page 26). a target is disabled when ce# is driven high, even when it is busy. all of the target's signals are disabled exce pt ce#, wp#, and r/b#. after the target is disabled, clk can be stopped. a target enters low-power standby when it is di sabled and is not busy. if the target is busy when it is disabled, the target enters standb y after all of the luns complete their opera- tions. synchronous bus idle/driving a target's bus is idle or driving when: ? clk is running, ?ce# is low, ?ale is low, and ?cle is low. the bus is idle when w/r# transitions high and is latched by clk. during the bus idle mode, all signals are enabled; dqs and dq[7:0] are inputs. no commands, addresses, or data are latched into the target; no data is output. when entering the bus idle mode, the host must wait a minimum of t cad before changing the bus mode. in the bus idle mode, the only valid bus modes supported are: bus driving, command, address, and ddr data input. the bus is driving when w/r# transitions low and is latched by clk. during the bus driving mode, all signals are enabled; dqs is low and dq[7:0] is driven low or high, but no valid data is output. following the bus driving mode, the only valid bus modes supported are bus idle and ddr data output.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 27 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 20: synchronous bus idle/driving behavior notes: 1. only the selected lun drives dqs and dq[7 :0]. during a multi-lun operation, the host must use the select lun with status (78h) to prevent data output contention. ce# cle ale clk w/r# dqs dq[7:0] undefined (driven by nand) t cals t dqsd t dqshz t cals bus idle bus idle bus driving
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 28 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance synchronous commands a command is written from dq[7:0] to the co mmand register on th e rising edge of clk when: ?ce# is low, ?ale is low, ?cle is high, and ? w/r# is high. after a command is latched, and prior to issuing the next command, address, or data i/o, the bus must go to the bus idle mode on the next rising edge of clk, except when the clock period, t ck, is greater than t cad. commands are typically ignored by luns that are busy; however, some commands, such as read status (70h) and select lun with status (78h), are accepted by luns, even when they are busy (see table 5 on page 39). figure 21: synchronous command cycle notes: 1. when ce# remains low, t cad begins at the rising edge of the clock from which the com - mand cycle is latched for subsequent command, ad dress, data input, or data output cycle(s). clk ale cle dqs dq[7:0] t ckl t calh t cah t cas t cals t calh t cals dont care t ckh t calh t cals t cals ce# t ch t cs t cad starts here 1 t cad w/r# t ck t calh t cals t dqshz command undefined
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 29 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance synchronous addresses a synchronous address is written from dq[7:0] to the address register on the rising edge of clk when: ?ce# is low, ?ale is high, ?cle is low, and ? w/r# is high. after an address is latched, and prior to issu ing the next command, address, or data i/o, the bus must go to the bus idle mode on the next rising edge of clk, except when the clock period, t ck, is greater than t cad. bits not part of the address space must be lo w (see table 2 on page 23). the number of address cycles required for each command varies. refer to the command descriptions to determine addressing requirem ents (see table 5 on page 39). addresses are typically ignored by luns that are busy; however, some addresses such as address cycles that follow the select lun with status (78h) command, are accepted by luns, even when they are busy (see table 5 on page 39). figure 22: synchronous address cycle notes: 1. when ce# remains low, t cad begins at the rising edge of the clock from which the com - mand cycle is latched for subsequent command, ad dress, data input, or data output cycle(s). clk ale cle dqs dq[7:0] t ckl t calh t cals t calh t cals dont care undefined t ckh t cals t calh t cals t calh t cals ce# t ch t cs t cad w/r# t ck t dqshz t cah t cas address t cad starts here 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 30 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance synchronous ddr data input to enter the ddr data input mode, th e following conditions must be met: ? clk is running, ?ce# is low, ? w/r# is high, ? t cad is met, ?dqs is low, and ? ale and cle are high on the rising edge of clk. upon entering the ddr data input mode after t dqss, data is written from dq[7:0] to the cache register on each and every rising and falling edge of dqs (center-aligned) when: ? clk is running and the dqs-to-clk skew meets t dsh and t dss, ?ce# is low, ? w/r# is high, and ? ale and cle are high on the rising edge of clk. to exit ddr data input mode the following conditions must be met: ? clk is running and the dqs-to-clk skew meets t dsh and t dss, ?ce# is low, ? w/r# is high, ? ale and cle are latched low on the rising edge of clk, ? the final two data bytes of the data input sequence are written from dq[7:0] to the cache register on the final rising and falling edges of dqs after the last cycle in the data input sequence ale and cle are latched high, and ? after the final falling edge of dqs, it is held low for t wpst. following t wpst, the bus enters bus idle mode and t cad begins on the next rising edge of clk. after t cad starts, the host can disable the target if desired. data input is ignored by luns that are not selected or are busy.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 31 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 23: synchronous ddr data input cycles notes: 1. when ce# remains low, t cad begins at the first risi ng edge of the clock after t wpst com - pletes. 2. t dsh (min) generally occurs during t dqss (min). 3. t dss (min) generally occurs during t dqss (max). clk ale cle dq[7:0] dqs t ckl t calh t dh t ds t dqss t cals t calh t cals dont care t ckh t calh t cals t cals t calh t cals t cals ce# t ch t cs t cad w/r# t ck t dqsl t wpre t dqsl t dqsh t dqsh t dqsh t wpst d n-1 d 2 t dsh t dsh t dss t dsh t dss t dsh t dss t dh t ds d 3 d n-2 d n d 0 d 1 t cad starts here 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 32 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance synchronous ddr data output data can be output from a lun if it is ready. data output is supported following a read operation from the nand flash array. to enter the ddr data output mode, the following conditions must be met: ? clk is running, ?ce# is low, ? the host has released the dq[7:0] bus and dqs, ? w/r# is latched low on the rising edge of clk to enable the selected lun to take ownership of the dq[7:0] bus and dqs within t wrck, ? t cad is met, and ? ale and cle are high on the rising edge of clk. upon entering the ddr data output mode, dq s will toggle high and low with a delay of t dqsck from the respective rising and fallin g edges of clk. dq[7:0] will output data edge-aligned to the rising and falling edges of dqs, with the first transition delayed by no more than t ac. ddr data output mode continues as long as: ? clk is running, ?ce# is low, ? w/r# is low, and ? ale and cle are high on the rising edge of clk. to exit ddr data output mode, the following conditions must be met: ? clk is running, ?ce# is low, ? w/r# is low, and ? ale and cle are latched low on the rising edge of clk. the final two data bytes will be output on dq [7:0] on the final rising and falling edges of dqs. the final rising and falling edges of dqs occur t dqsck after the last cycle in the data output sequence where ale and cle are latched high. after t ckwr, the bus enters bus idle mode, and t cad begins on the next ri sing edge of clk. after t cad starts, the host can disable the target if desired. data output requests are typically ignored by a lun that is busy; however, it is possible to output data from the status register ev en when a lun is busy by issuing the read status (70h) or select lun with status (78h) command.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 33 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance figure 24: synchronous ddr data output cycles notes: 1. when ce# remains low, t cad begins at the rising edge of the clock after t ckwr for subse - quent command or data output cycle(s). 2. see figure 21 on page 28 for details of w/r# behavior. 3. t ac is the dq output window relative to clk and is the long-term component of dq skew. 4. for w/r# transitioning high: dq[7:0] and dqs go to tri-state. 5. for w/r# transitioning low: dq[7:0] drives current state and dqs goes low. 6. after final data output, dq[7:0] is driven until w/r# goes high, but is not valid. clk ale cle dq[7:0] dqs t ckl t calh t cals t clh t cals dont care t ckh t alh t cals t cals t calh t cals t cals t cals t cals ce# t ch t cs t cad t dqsd t wrck t dqsck t ac w/r# t dqsck t dqsck t ckwr t dqsck t dqsck t dqsck t dqshz t dqsq t qh t dqsq t ck t hp t hp t hp t hp t hp t hp data transitioning t dvw t qh t dvw t qh t dvw t qh t dvw t dvw t cad starts here 1 undefined (driven by nand) d 0 d 1 d 2 d n-1 d n-2 d n t dqsq t dqsq
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 34 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory bus operation micron confidential and proprietary advance write protect see ?write protect (wp#)? on page 21 under ?asynchronous interface?. ready/busy# see ?ready/busy# (r/b#)? on page 21 under ?asynchronous interface?.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 35 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory vcc power cycling micron confidential and proprietary advance vcc power cycling high-speed nand flash devices are designed to prevent data corruption during power transitions. vcc is internally monitored. (the wp# signal supports additional hardware protection during power transitions.) when ramping v cc and v cc q, use the following procedure to initialize the device: 1. ramp v cc to 2.7?3.6v. 2. ramp v cc q to min-max no sooner than v cc . v cc q and v cc may ramp at the same time. 3. the host must wait for r/b# to be valid and high before issuing reset (ffh) to any target (see figure 26 on page 36 ). the r/b# signal becomes valid when: 3a. 50s has elapsed since the beginning the v cc ramp, and 3b. 10s has elapsed since v cc /v cc q reached min. 4. if not monitoring r/b#, the host must wait at least 100s after vcc/v cc q reaches min. 5. all of the targets on the device power on with the asynchronous interface active. each nand flash lun draws less than an averag e of 10ma (ist) measured over intervals of 1ms until the reset (ffh) command is issued. 6. the reset (ffh) command must be the firs t command issued to all targets (ce#s) after the nand flash device is powered on. each target will be busy for a maximum of t por after a reset command is issued. the reset busy time can be monitored by polling r/b# or issuing the read status ( 70h) command to poll the status register. 7. the device is now initialized and ready for normal operation. at power-down, v cc q must go low, either before, or simultaneously with, v cc going low. figure 25: power cycle notes: 1. vcc is exaggerated over vccq in this figure for illustrative purposes. v cc q (min) v cc (min) v cc q v cc supply voltage command input prohibited command input prohibited time
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 36 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory vcc power cycling micron confidential and proprietary advance figure 26: r/b# power-on behavior reset (ffh) is issued 50s (min) 100s (max) 10s (max) ! 0s (max ) vcc ramp starts vccq vcc r/b# vccq = vccq (min) vcc = vcc (min)
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 37 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory activating interfaces micron confidential and proprietary advance activating interfaces after performing the steps under ?vcc power cycling? on page 35, the asynchronous interface is active for a ll targets on the device. each target's interface is independent of ot her targets, so the host is responsible for changing the interface for each target. if the host and nand flash device, through error, are no longer using the same interface, then steps under "activating the asynchrono us interface" are performed to resynchro- nize the interfaces. activating the asynchronous interface to activate the asynchronous nand interface, the following steps are repeated for each target: 1. the host pulls ce# high, disables its in put to clk, and enables its asynchronous interface. 2. the host pulls ce# low and issues the reset (ffh) command, using an asynchro - nous command cycle. 3. r/b# goes low for t rst. 4. after t itc, and during t rst, the device enters the asynchronous nand interface. read status (70h) and select lun with status (78h) are the only commands that can be issued. 5. after t rst, r/b# goes high. timing mode feature address (01h), sub-feature parameter p1 is set to 00h, indicating that the asynchronous nand interface is active and that the device is set to timing mode 0. for further details, see ?reset (ffh)? on page 41. activating the synchronous interface to activate the synchronous na nd flash interface, the following steps are repeated for each target: 1. issue the set features (efh) command. 2. write address 01h, which selects the timing mode. 3. write p1 with 1xh, where "x" is the timi ng mode used in the synchronous interface (see ta b l e 10 on page 54 ). 4. write p2?p4 as 00h-00h-00h. 5. r/b# goes low for t itc. the host should pull ce# high. during t itc, the host should not issue any type of command, including status commands, to the nand flash device. 6. after t itc, r/b# goes high and the synchronou s interface is enabled. before pulling ce# low, the host should enable the clock.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 38 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory activating interfaces micron confidential and proprietary advance figure 27: activating the synchronous interface notes: 1. tm = timing mode. cycle type dqx sr[6] cmd addr din din din din efh 01h tm p2 p3 p4 t adl t wb t cad ce# may transitions high ce# may transition low 100 ns t itc a b c
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 39 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance command definitions table 5: command set command command cycle #1 # valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 valid while other luns are busy 2 notes reset operations reset ffh 0 ? ? yes yes synchronous reset fch 0 ? ? yes yes identification operations read id 90h 1 ? ? 3 read parameter page ech 1 ? ? read unique id edh 1 ? ? configuration operations get features eeh 1 ? ? 3 set features efh 1 4 ? 4 status operations read status 70h 0 ? ? yes select lun with status 78h 3 ? ? yes yes column address operations change read column 05h 2 ? e0h yes select cache register 06h 5 ? e0h yes change write column 85h 2 optional ? yes change row address 85h 5 optional 11h yes 8 read operations read mode 00h 0 ? ? yes read page 00h 5 ? 30h yes 5 read page multi-plane 00h 5 ? 32h yes read page cache sequential 31h 0 ? ? yes 6 read page cache random 00h 5 ? 31h yes 5, 6 read page cache last 3fh 0 ? ? yes 6 program operations program page 80h 5 yes 10h yes program page multi- plane 80h 5 yes 11h yes program page cache 80h 5 yes 15h yes 7 erase operations erase block 60h 3 ? d0h yes erase block multi-plane 60h 3 ? d1h yes copyback operations copyback read 00h 5 ? 35h yes 5 copyback program 85h 5 optional 10h yes
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 40 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance notes: 1. busy means rdy = "0". 2. these commands can be used for multi-lun operations (see ?multi-lun operations? on page 86 ). 3. the read id (90h) and get features (eeh) outp ut identical data on rising and falling dqs edges. 4. the set features (efh) command requires data transition prior to the rising edge of clk, with identical data for th e rising and falling edges. 5. this command can be preced ed by up to one read page multi-plane (00h-32h) command to accommodate a maximum simultan eous two-plane array operation. 6. issuing a read page cache-seri es (31h, 00h-31h, 00h-32h, 3fh) command when the array is busy (rdy = "1", ardy = "0") is supporte d if the previous command was a read page (00h-30h) or read page cache-series command; otherwise it is prohibited. 7. issuing a program page cache (80h-15h) comma nd when the array is busy (rdy = "1", ardy = "0") is supported if the previous command was a program page cache (80h-15h) command; otherwise it is prohibited. 8. command cycle #2 of 11h is conditional. see ?change row address (85h)? for more details. copyback program multi-plane 85h 5 optional 11h yes table 5: command set (continued) command command cycle #1 # valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 valid while other luns are busy 2 notes
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 41 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance reset operations reset (ffh) the reset (ffh) command is used to put a target into a known condition and to abort command sequences in progress. this comman d is accepted by all luns, even when they are busy. when ffh is written to the command register, the target goes busy for t rst. during t rst, the selected target (ce#) discontinues all array operations on all luns. all pending single-plane and multi-plane operations are ca ncelled. if this command is issued while a program or erase operation is occurring on one or more luns, the data may be partially programmed or erased and is invalid. the command register is cleared and ready for the next command. the data regist er and cache register contents are invalid. if the reset (ffh) command is issued when the synchronous interface is enabled, the target's interface is changed to the asynchrono us interface and the timing mode is set to ?0?. the reset (ffh) command can be issued asynchronously when the synchronous interface is active, meaning th at clk does not need to be continuously running when ce# is transitioned low and ffh is latched on the rising edge of clk. after this command is latched, the host shou ld not issue any commands during t itc. after t itc, and during or after t rst, the host can poll each lun's status register. if the reset (ffh) command is issued when the asynchronous interface is active, the target's asynchronous timing mode remains unchanged. during or after t rst, the host can poll each lun's status register. reset must be issued as the first command to each target following power-up (see ?vcc power cycling? on page 35). use of the select lun with status (78h) command is prohibited during the power-on reset. to determine when the target is ready, use read status (70h). figure 28: asynchronous reset (ffh) cycle cle ce# we# r/b# i/ox (dqx) t rst t wb ffh reset command
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 42 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance synchronous reset (fch) when the synchronous interface is acti ve, the synchronous reset (fch) command is used to put a target into a known condition and to abort a command sequence in progress. this command is accepted by all luns, even when they are busy. when fch is written to the command register, the target goes busy for t rst. during t rst, the selected target (ce#) discontinues all array operations on all luns. all pending single-plane and multi-plane operations are ca ncelled. if this command is issued while a program or erase operation is occurring on one or more luns, the data may be partially programmed or erased and is invalid. the command register is cleared and ready for the next command. the data register and cache register contents are invalid, and the synchronous interface remains active. during or after t rst, the host can poll each lun's status register. synchronous reset is only accepted while the synchronous interface is active. its use is prohibited when the asynchronous interface is active. figure 29: synchronous reset (fch) cycle clk ale cle dqs dq[7:0] r/b# t calh t cah t cas t cals t calh dont care t calh t cals t rst ce# t ch t cs t cad t wb w/r# fch synchronous reset command
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 43 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance identification operations read id (90h) the read id (90h) command is used to re ad identifier codes programmed into the target. this command is accepted by the target only when all luns on the target are idle. writing 90h to the command register puts the ta rget in read id mode. the target stays in this mode until another valid command is issued. when the 90h command is followed by an 00h address cycle, the target returns a 5-byte identifier code that includes the manufact urer's id, device configuration, and part- specific information. when the 90h command is followed by a 20h address cycle, the target returns the 4-byte onfi identifier code. after the 90h and address cycle are written to the target, the host enables data output mode to read the identifier information. when the asynchronous interface is active, one data byte is output per re# toggle. when th e synchronous interface is active, one data byte is output per rising edge of dqs when ale and cle are high; the data byte on the falling edge of dqs is identical to the data byte output on the previous rising edge of dqs. figure 30: read id (90h) with 00h address cycle operation notes: 1. see table 6 on page 43 for byte definitions. figure 31: read id (90h) with 20h address cycle operation notes: 1. see table 7 on page 44 for byte definitions. table 6: read id parameters for address 00h options i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) value notes byte 0 ? manufacturer id manufacturer micron 001011002ch1 byte 1 ? device id vcc 3.3v 1000 c y c le type i/o[7:0] (dq[7:0]) t whr c omman d 90h 00h byte 0 byte 1 byte 2 byte 3 a dd ress d out d out d out d out d out byte 4 cycle type i/o[7:0] (dq[7:0]) t whr command 90h 20h 4fh 4eh 46h 49h address d out d out d out d out
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 44 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance notes: 1. h = hexadecimal; b = binary notes: 1. h = hexadecimal read parameter page (ech) the read parameter page (ech) command is used to read the onfi parameter page programmed into the target. this command is accepted by the target only when all luns on the target are idle. writing ech to the command register puts th e target in read parameter page mode. the target stays in this mode until another valid command is issued. density per ce# 8gb 0010 byte value mt29f8g 0010100028h byte 2 luns per ce# 1 0 0 00b cell type slc 0 0 00b reserved 0000 0000b byte value mt29f8g 0000000000h byte 3 page size 4kb 1 0 10b spare area size per 512b 28b 0 1 01b pages per block 128 010 010b multi-lun operations not supported 00b supported 11b byte value mt29f8g 0010011026h byte 4 planes per lun 2 0 1 01b blocks per lun 2,048 001 001b timing mode: asynchronous 4 (25ns) 100 100b byte value mt29f8g 1000010185h table 7: read id parameters for address 20h byte options i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) value notes 0 ?o? 010011114fh 1 1 ?n? 010011104eh 2 ?f? 0100011046h 3 ?i? 0100100149h 4 undefinedxxxxxxxxxxh table 6: read id parameters for address 00h (continued) options i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) value notes
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 45 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance when the ech command is followed by an 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. use of the select lun with status (78h) command is prohibited while the target is busy and during data output. after t r completes, the host enables data output mode to read the parameter page. when the asynchronous interface is active, on e data byte is output per re# toggle. when the synchronous interface is active, one data byte is output for each rising or falling edge of dqs. a minimum of seven copies of the parameter page are stored in the device. each param- eter page is 256 bytes. if desired, the change read column (05h-e0h) command can be used to change the location of data output. use of the select cache register (06h-e0h) is prohibited. figure 32: read parameter page (ech) operation cycle type i/o[7:0] (dq[7:0]) r/b# t wb t r t rr command address d out ech 00h p0 0 p1 0 d out d out p0 1 d out d out p1 1 d out
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 46 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance table 8: parameter page data structure byte description device values revision information and features block 0?3 parameter page signature byte 0: 4fh, ?o? byte 1: 4eh, ?n? byte 2: 46h, ?f? byte 3: 49h, ?i? ? 4fh, 4eh, 46h, 49h 4?5 revision number bit[15:3]: reserved (0) bit 2: 1 = supports onfi version 2.0 bit 1: 1 = supports onfi version 1.0 bit 0: reserved (0) ? 06h, 00h 6?7 features supported bit[15:6]: reserved (0) bit 5: 1 = supports synchronous interface bit 4: 1 = supports odd-to-even page copyback bit 3: 1 = supports interlea ved (multi-plane) operations bit 2: 1 = supports non-sequential page programming bit 1: 1 = supports multiple lun operations bit 0: 1 = supports 16-bit data bus width mt29f8g08cbaba 18h, 00h mt29f8g08cbcbb 38h, 00h 8?9 optional commands supported bit[15:6]: reserved (0) bit 5: 1 = supports read unique id bit 4: 1 = supports internal data move bit 3: 1 = supports two-plane/multiple-die read status bit 2: 1 = supports get features and set features bit 1: 1 = supports read cache commands bit 0: 1 = supports program page cache mode command ? 3fh, 00h 10?31 reserved (0) ? all 00h manufacturer information block 32?43 device manufacturer (12 ascii characters) micron ? 4dh, 49h, 43h, 52h, 4fh, 4eh, 20h, 20h, 20h, 20h, 20h, 20h 44?63 device model (20 ascii characters) note: for tsop packaged devices with wp or wc package codes, only the wp package code will be referenced in the read parameter page. mt29f8g08ababawp 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 42h, 41h, 42h, 41h, 57h, 50h, 20h, 20h, 20h, 20h MT29F8G08ABCBBwp 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 42h, 43h, 42h, 42h, 57h, 50h, 20h, 20h, 20h, 20h mt29f8g08ababac3 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 42h, 41h, 42h, 41h, 43h, 32h, 20h, 20h, 20h, 20h MT29F8G08ABCBBh1 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 42h, 43h, 42h, 42h, 48h, 31h, 20h, 20h, 20h, 20h
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 47 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance 64 jedec manufacturer id ? 2ch 65?66 date code ? 00h, 00h 67?79 reserved (0) ? all 00h memory organization block 80?83 number of data bytes per page ? 00h, 10h, 00h, 00h 84?85 number of spare bytes per page ? e0h, 00h 86?89 number of data bytes per partial page ? 00h, 02h, 00h, 00h 90?91 number of spare bytes per partial page ? 1ch, 00h 92?95 number of pages per block ? 80h, 00h, 00h, 00h 96?99 number of blocks per lun ? 00h, 08h, 00h, 00h 100 number of luns per chip enable ? 01h 101 number of address cycles bit[7:4]: column address cycles bit[3:0]: row address cycles ? 23h 102 number of bits per cell ? 01h 103?104 bad blocks maximum per lun ? 28h, 00h 105?106 block endurance ? 01h, 05h 107 guaranteed valid blocks at beginning of target ? 01h 108?109 block endurance for guaranteed valid blocks ? 00h, 00h 110 number of programs per page ? 04h 111 partial programming attributes bit[7:5]: reserved bit 4: 1 = partial page layout is partial page data followed by partial page spare bits [3:1]: reserved bit 0: 1 = partial page programming has constraints ? 00h 112 number of bits ecc correctability ? 04h 113 number of interleaved address bits bit[7:4]: reserved (0) bit[3:0]: number of in terleaved address bits ? 01h 114 interleaved operation attributes bit[7:4]: reserved (0) bit 3: address restrict ions for program cache bit 2: 1 = program cache supported bit 1: 1 = no block address restrictions bit 0: overlapped/concu rrent interleaving support ? 0eh 115?127 reserved (0) ? all 00h electrical parameters block 128 i/o pin capacitance per chip enable ? 05h table 8: parameter page data structure (continued) byte description device values
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 48 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance 129?130 timing mode support bit[15:6]: reserved (0) bit 5: 1 = supports timing mode 5 bit 4: 1 = supports timing mode 4 bit 3: 1 = supports timing mode 3 bit 2: 1 = supports timing mode 2 bit 1: 1 = supports timing mode 1 bit 0: 1 = supports timing mode 0, shall be 1 ? 1fh, 00h 131?132 program cache timing mode support bit[15:6]: reserved (0) bit 5: 1 = supports timing mode 5 bit 4: 1 = supports timing mode 4 bit 3: 1 = supports timing mode 3 bit 2: 1 = supports timing mode 2 bit 1: 1 = supports timing mode 1 bit 0: 1 = supports timing mode 0 ? 1fh, 00h 133?134 t prog maximum program page time (s) ? f4h, 01h 135?136 t bers maximum block erase time (s) ? b8h, 0bh 137?138 t r maximum page read time (s) ? 19h, 00h 139?140 t ccs minimum change co lumn setup time (ns) ? c8h, 00h 141?142 source synchronous timing mode support bit[15:5]: reserved (0) bit 4: 1 = supports timing mode 4 bit 3: 1 = supports timing mode 3 bit 2: 1 = supports timing mode 2 bit 1: 1 = supports timing mode 1 bit 0: 1 = supports timing mode 0 mt29f8g08ababa 00h, 00h MT29F8G08ABCBB 1fh, 00h 143 source synchronous features bit[7:2]: reserved (0) bit 1: 1 = typical capacitance values present bit 0: 0 = use t cad min value mt29f8g08ababa 00h MT29F8G08ABCBB 02h 144?145 clk input pin capacitance per chip enable, typical mt29f8g08ababawp 00h, 00h mt29f8g08ababac3 MT29F8G08ABCBBwp 3fh, 00h MT29F8G08ABCBBh1 24h, 00h 146?147 i/o pin capacitance per chip enable, typical mt29f8g08ababawp 00h, 00h mt29f8g08ababac3 MT29F8G08ABCBBwp 1ch, 00h MT29F8G08ABCBBh1 2dh, 00h 148?149 input capacitance per chip enable, typical mt29f8g08ababawp 00h, 00h mt29f8g08ababac3 MT29F8G08ABCBBwp 3fh, 00h MT29F8G08ABCBBh1 28h, 00h 150 input pin capacitance per chip enable, maximum mt29f8g08ababawp 0ah mt29f8g08ababac3 MT29F8G08ABCBBwp MT29F8G08ABCBBh1 05h table 8: parameter page data structure (continued) byte description device values
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 49 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance 151 driver strength support bit[7:3]: reserved (0) bit 2: 1 = supports overdrive (2 drive strength) bit 1: 1 = supports overdrive (1 drive strength) bit 0: 1 = supports driver strength settings ? 07h 152-163 reserved (0) ? all 00h vendor block 164?165 vendor-specific revision number ? 01h, 00h 166 two-plane page read support bit[7:1]: reserved (0) bit 0: 1 = support for two-plane page read ? 01h 167 read cache support bit[7:1]: reserved (0) bit 0: 0 = does not support micron-specific read cache function ? 00h 168 read unique id support bit[7:1]: reserved (0) bit 0: 0 = does not support micron-specific read unique id ? 00h 169 programmable i/o drive strength support bit[7:1]: reserved (0) bit 0: 0 = no support for programmable i/o drive strength by b8h command ? 00h 170 number of programmable i/o drive strength settings bit[7:3]: reserved (0) bit [2:0] = number of prog rammable i/o drive strength settings ? 04h 171 programmable i/o drive strength feature address bit[7:0] = programmable i/o drive strength feature address ? 10h 172 programmable r/b# pull -down strength support bit[7:1]: reserved (0) bit 0: 1 = support programmable r/b# pull-down strength ? 01h 173 programmable r/b# pull-down strength feature address bit[7:0] = feature address used with programmable r/ b# pull-down strength ? 81h 174 number of programmable r/b# pull-down strength settings bit[7:3]: reserved (0) bit[2:0] = number of programmable r/b# pull-down strength settings ? 04h 175 otp mode support bit[7:2]: reserved (0) bit 0: 0 = does not support otp mode bit 1: 1 = supports get/se t features command set bit 0: 0 = does not support a5h/a0h/afh otp command set ? 02h table 8: parameter page data structure (continued) byte description device values
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 50 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance 176 otp page start bit[7:0] = page where otp page space begins ? 02h 177 otp data protect address bit[7:0] = page address to use when issuing otp data protect command ? 01h 178 number of otp pages bit[15:4]: reserved (0) bit[3:0] = number of otp pages ? 1eh 179 otp feature address ? 90h 180?252 reserved (0) ? all 00h 253 parameter page revision ? 01h 254?255 integrity crc mt29f8g08ababawp 92h, 15h mt29f8g08ababac3 46h, 07h MT29F8G08ABCBBwp a9h, 1fh MT29F8G08ABCBBh1 a7h, 20h redundant parameter pages 256?511 value of bytes 0?255 ? see bytes 0?255 512?767 value of bytes 0?255 ? see bytes 0?255 768?1,023 value of bytes 0?255 ? see bytes 0?255 1,024? 1,279 value of bytes 0?255 ? see bytes 0?255 1,278? 1,535 value of bytes 0?255 ? see bytes 0?255 1,536? 1,791 value of bytes 0?255 ? see bytes 0?255 1,792? 2,047 value of bytes 0?255 ? see bytes 0?255 2,048? 2,303 value of bytes 0?255 ? see bytes 0?255 2,304? 2,559 value of bytes 0?255 ? see bytes 0?255 2,560? 2,815 value of bytes 0?255 ? see bytes 0?255 2,816? 3,071 value of bytes 0?255 ? see bytes 0?255 3,072? 3,327 value of bytes 0?255 ? see bytes 0?255 3,328? 3,583 value of bytes 0?255 ? see bytes 0?255 3,584? 4,095 value of bytes 0?255 ? see bytes 0?255 4,096? 4,319 reserved (ffh) ? all ffh table 8: parameter page data structure (continued) byte description device values
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 51 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance read unique id (edh) the read unique id (edh) command is used to read a unique identifier programmed into the target. this command is accepted by the target only when all luns on the target are idle. writing edh to the command register puts the target in read unique id mode. the target stays in this mode until another valid command is issued. when the edh command is followed by an 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. after t r completes, the host enables data output mode to read the unique id. when the asynchronous interface is active, one data byte is output per re# toggle. when the synchronous interface is active, two data byte s are output, one byte for each rising or falling edge of dqs. sixteen copies of the unique id data are stored in the device. each copy is 32 bytes. the first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple- ment of the first 16 bytes. the host should xor the first 16 bytes with the second 16 bytes. if the result is 16 bytes of ffh, then th at copy of the unique id data is correct. in the event that a non-ffh result is returned, the host can repeat the xor operation on a subsequent copy of the unique id data. if desired, the change read column (05h- e0h) command can be used to change the data output location. use of the select cache register (06h-e0h) command is prohibited. figure 33: read uniq ue id (edh) operation cycle type i/o[7:0] (dq[7:0]) r/b# t wb t r t rr command address d out edh 00h u0 0 u1 0 d out d out u0 1 d out d out u1 1 d out
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 52 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance configuration operations the get features (eeh) and set features (efh) commands are used to modify the target's default power-on behavior. these commands use a one-byte feature address to determine which sub-feature parameters will be read or modified. each feature address (in the 00h to ffh range) is defined in table 9. the get features command reads the sub-feature parameters (p1-p4) at the spec ified feature address. the set features (efh) command writes sub-feature parameters (p1-p4) to the specified feature address. set features efh the set features (efh) command writes th e sub-feature parameters (p1-p4) to the specified feature address to enable or disable target-specific features. this command is accepted by the target only when all luns on the target are idle. writing efh to the command register puts the target in the set features mode. the target stays in this mode until another command is issued. the efh command is followed by a valid feature address as specified in table 9 on page 52. the host waits for t adl before the sub-feature parameters are input. when the asynchronous interface is active, one sub-feature parameter is latched per rising edge of we#. when the synchronous interface is ac tive, one sub-feature parameter is latched per rising edge of dqs. the data on the falling edge of dqs should be identical to the sub-feature parameter input on the previous rising edge of dqs. after all four sub-feature parameters are input, the target goes busy for t feat. the read status (70h) command can be used to monitor for command completion. feature address 01h (timing mode) operation is unique. if set features is used to modify the interface type, the target will be busy for t itc. see ?activating interfaces? on page 37 for details. table 9: feature address definitions feature address definition 00h reserved 01h timing mode 02h?0fh reserved 10h programmable output drive strength 11h?7fh reserved 80h programmable output drive strength 81h programmable rb# pull-down strength 82h?8fh reserved 90h array operation mode 91h?ffh reserved
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 53 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance figure 34: set features (efh) operation get features (eeh) the get features (eeh) command reads the sub-feature parameters (p1-p4) from the specified feature address. this command is accepted by the target only when all luns on the target are idle. writing eeh to the command register puts th e target in get features mode. the target stays in this mode until another valid command is issued. when the eeh command is followed by a feature address, the target goes busy for t feat. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. during and prior to data output, use of the select lun with status (78h) command is prohib- ited prior to and during data output. after t feat completes, the host enables data output mode to read the sub-feature parameters. when the asynchronous interface is active, one data byte is output per re# toggle. when the synchronous interface is ac tive, two data bytes are output per toggle, one byte for each rising or falling edge of dqs. figure 35: get features (eeh) operation cycle type i/o[7:0] (dq[7:0]) r/b# t adl command address efh fa d in d in d in d in p1 p2 p3 p4 t wb t feat cycle type i/ox (dqx) r/b# t wb t feat t rr command address d out eeh fa p1 p2 d out d out p3 p4 d out
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 54 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance notes: 1. asynchronous timi ng mode 0 is the default, power-on value. notes: 1. see ?output drive strength? on page 89 for details. table 10: feature address 01h: timing mode sub-feature parameter options i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) value note s p1 timing mode mode 0 (default) 0000x0h1 mode 1 0001x1h mode 2 0010x2h mode 3 0011x3h mode 4 0100x4h data interface asynchronous (default) 00 0xh1 synchronous ddr 01 1xh reserved 1x 2xh reserved 00 00b p2 reserved 0000000000h p3 reserved 0000000000h p4 reserved 0000000000h table 11: feature addresses 10h and 80h: programmable output drive strength sub-feature parameter options i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) value notes p1 output drive strength overdrive 2 0 0 00h 1 overdrive 1 0 1 01h nominal (default) 1 0 02h underdrive 1 1 03h reserved 000000 00h p2 reserved 0000000000h p3 reserved 0000000000h p4 reserved 0000000000h
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 55 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance notes: 1. this feature address is used to change the default r/b# pull-down strength. its strength should be selected based on the expected lo ading of r/b#. full strength is the default, power-on value. notes: 1. see ?one-time programmable (otp) operations? on page 82 for details. table 12: feature addresses 81h: programmable r/b# pull-down strength sub-feature parameter options i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) value notes p1 r/b# pull-down strength full (default) 0 0 00h 1 three-quarter 0 1 01h one-half 1 0 02h one-quarter 1 1 03h reserved 000000 00h p2 reserved 0000000000h p3 reserved 0000000000h p4 reserved 0000000000h table 13: feature addresses 90h: array operation mode sub-feature parameter options i/o7 (dq7) i/o6 (dq6) i/o5 (dq5) i/o4 (dq4) i/o3 (dq3) i/o2 (dq2) i/o1 (dq1) i/o0 (dq0) value notes p1 array operation mode normal (default) 0 00h otp block 1 01h 1 reserved 0000000 00h p2 reserved 0000000000h p3 reserved 0000000000h p4 reserved 0000000000h
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 56 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance status operations each lun provides its status independently of other luns on the same target through its 8-bit status register. after the read status (70h) or select lun with status (78h) command is issued, status register output is enabled. the cont ents of the status register are returned on i/o[7:0], dq[7:0] for each data output request. when the asynchronous interface is active and status register output is enabled, changes in the status register are seen on i/o[7:0], dq[7:0] as long as ce# and re# are low; it is not necessary to toggle re# to see the status register update. when the synchronous interface is active and status register output is enabled, changes in the status register are seen on i/o[7:0], dq[7:0] as long as ce# and w/r# are low and ale and cle are high. dqs also toggles while ale and cle are high. while monitoring the status register to determine when a data transfer from the flash array to the data register ( t r) is complete, the host must issue the read mode (00h) command to disable the status register and enable data output (see read mode 00h on page 55). the read status (70h) command returns the st atus of the most recently selected lun. to prevent data contention during or foll owing a multi-lun operation, the host must enable only one lun for status output by using the select lun with status (78h) command (see ?multi-lun operations? on page 86). table 14: status register definition sr bit definition independent per plane 1 description 7 wp# ? write protect: "0" = protected "1" = not protected in the normal array mode, this bit indica tes the value of the wp# signal. in otp mode this bit is set to "0" if a prog ram otp page operation is attempted and the otp area is protected. 6 rdy ? ready/busy i/o: "0" = busy "1" = ready this bit indicates th at the selected lun is not ava ilable to accept new commands, address, or data i/o cycles with the exception of reset (ffh), synchronous reset (fch), read status (70h), and sele ct lun with status (78h). this bit applies only to the selected lun. 5 ardy ? ready/busy array: "0" = busy "1" = ready this bit goes low (busy) when an array operation is occurring on any plane of the selected lun. it goes high when all array operations on the selected lun finish. this bit applies only to the selected lun. 4 ?? reserved (0) 3 ?? reserved (0) 2 ?? reserved (0)
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 57 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance notes: 1. after a multi-plane operation begins, the failc and fail bits are ored together for the active planes when the read status (70h) command is issued . after the select lun with status (78h) command is issued , the failc and fail bits refl ect the status of the plane selected. read status (70h) the read status (70h) command returns th e status of the last-selected lun on a target. this command is accepted by the last-selected lun even when it is busy (rdy = 0). if there is only one lun per target, the re ad status (70h) command can be used to return status following any nand command. in devices that have more than one lun per target, during and following multi-lun operations, the select lun with status (7 8h) command must be used to select the lun that should report status. in this situ ation, using the read status (70h) command will result in bus contention, as two or more luns could respond until the next opera- tion is issued. the read status (70h) command can be used following all single-lun operations. figure 36: read status (70h) operation select lun with status (78h) the select lun with status (78h) command returns the status of the addressed lun on a target even when it is busy (rdy = 0). this command is accepted by all luns, even when they are busy (rdy = 0). 1 failc yes pass/fail (n-1): "0" = pass "1" = fail this bit is set if the previous operation on the selected lun failed. this bit is valid only when rdy (sr bit 6) is "1." it ap plies to program-, erase-, and copyback program-series operations (80h-10h, 80h- 15h, 60h-d0h, 85h-10h). this bit is not valid following a read-series operation. 0 fail yes pass/fail (n): "0" = pass "1" = fail this bit is set if the most recently finish ed operation on the selected lun failed. this bit is valid only when ardy (sr bit 5) is "1." it applies to program-, erase-, and copyback program-series operatio ns (80h-10h, 80h-15h, 60h-d0h, 85h- 10h). this bit is not valid following a read-series operation. table 14: status register definition (continued) sr bit definition independent per plane 1 description cycle type i/o[7:0] (dq[7:0]) t whr command d out 70h sr
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 58 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance writing 78h to the command register, followed by three row address cycles containing the page, block, and lun addresses, puts the selected lun into read status mode the selected lun stays in this mode until another valid command is issued. luns that are not addressed are deselected to avoid bus contention. the selected lun's status is returned when the host requests data output. the rdy and ardy bits of the status register are shared fo r all of the planes of the selected lun. the failc and fail bits are specific to the plane specified in the row address. the select lun with status (78h) command also enables the selected lun for data output. to begin data output following a read -series operation after the selected lun is ready (rdy = 1), issue the read mode (00h) command, then begin data output. if the host needs to change the cache register that will output data, use the select cache register (06h-e0h) command after the lun is ready (see ?select cache register (06h-e0h)? on page 59). use of the select lun with status (78h) command is prohibited during the power- on reset (ffh) command and when otp mode is enabled. it is also prohibited following some of the other reset, identification, and configuration operations. see individual operations for specific details. figure 37: select lun with status (78h) operation cycle type i/ox (dqx) t whr command address address address 78h r1 r2 r3 d out sr
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 59 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance column address operations the column address operations affect how data is input to and output from the cache registers within the target luns. these features provide host flexibility for managing data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register. when the asynchronous interface is active, column address operations can address any byte in the selected cache register. when the synchronous interface is active, column address operations are aligned to word boundaries (ca0 is forced to "0"), beca use as data is transferred on dq[7:0] in two- byte units. change read column (05h-e0h) the change read column (05h-e0h) comma nd changes the column address of the selected cache register and enables data ou tput from the last selected lun. this command is accepted by the selected lun when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected lun during cache read operations (rdy = 1; ardy = 0). writing 05h to the command register, followed by two column address cycles containing the column address, followed by the e0h command, puts the selected lun into data output mode. after the e0h command cycle is issued, the host must wait at least t ccs before requesting data output. the select ed lun stays in data output mode until another valid command is issued. in devices with more than one lun per ta rget, during and following multi-lun opera- tions, the select lun with status (78h) command must be issued prior to issuing the change read column (05h-e0h). in this situation, using the change read column (05h-e0h) command without the select lun status (78h) command will result in bus contention, as two or more luns could output data. figure 38: change read column (05h?e0h) operation select cache register (06h-e0h) the select cache register (06h-e0h) command enables data output on the addressed lun?s cache register at the specified column address. this command is accepted by a lun when it is ready (rdy = 1; ardy = 1). writing 06h to the command register, followed by two column address cycles and three row address cycles, followed by e0h, enable s data output mode on the address lun?s cache register at the specified column address. after the e0h command cycle is issued, the host must wait at least t ccs before requesting data output. the selected lun stays in data output mode until another valid command is issued. cycle type i/o[7:0] (dq[7:0]) sr[6] command address address 05h command e0h c1 c2 t ccs t rhw d out dk d out dk + 1 d out dk + 2 d out dn d out dn + 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 60 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance following a multi-plane read page operatio n, the select cache register (06h-e0h) command is used to select the cache register to be enabled for data output. after data output is complete on the selected plane, the command can be issued again to begin data output on another plane. in devices with more than one lun per target, after all of the luns on the target are ready (rdy = 1), the select cache register (06h-e0h) command can be used following a multi-lun read operation. luns that are not addressed are deselected to avoid bus contention. in devices with more than one lun per ta rget, during multi-lun operations where more than one or more luns are busy (rdy = 1; ardy = 0 or rdy = 0; ardy = 0), the select lun with status (78h) command must be issued to the target lun prior to issuing the select cache register (06h-e0h). in this situation, using the select cache register (06h-e0h) command without the select lun status (78h) command will result in bus contention, as two or more luns could output data. if there is a need to update the column addr ess without selecting a new cache register or lun, the change read column (05h-e0h) command can be used instead. figure 39: select cache register (06h?e0h) operation change write column (85h) the change write column (85h) command changes the column address of the selected cache register and enables data in put on the last-selected lun. this command is accepted by the selected lun when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected lun during cache program operations (rdy = 1; ardy = 0). writing 85h to the command register, followed by two column address cycles containing the column address, puts the selected lu n into data input mode. after the second address cycle is issued, the host must wait at least t ccs before inputting data. the selected lun stays in data input mode unti l another valid command is issued. though data input mode is enabled, data input from the host is optional. data input begins at the column address specified. the change write column (85h) command is supported prior to the final command cycle (10h, 11h, 15h) of the following commands: ? program page (80h-10h) ? program page multi-plane (80h-11h) ? program page cache (80h-15h) ? copyback program (85h-10h) ? copyback program multi-plane (85h-11h) in devices that have more than one lun per target, the change write column (85h) command can be used with other command s that support multi-lun operations. cycle type i/o[7:0] (dq[7:0]) command address address 06h command e0h c1 c2 address address r1 r2 address r3 t ccs t rhw d out dk d out dk + 1 d out dk + 2 d out dn d out dn + 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 61 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance figure 40: change write column (85h) operation change row address (85h) the change row address (85h) command changes the row address (block and page) where the cache register contents will be programmed in the nand flash array. it also changes the column address of the selected cache register and enables data input on the specified lun. this command is accept ed by the selected lun when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected lun during cache programming operations (rdy = 1; ardy = 0). writing 85h to the command register, then wr iting two column address cycles and three row address cycles, updates the page and bloc k destination of the s elected plane for the addressed lun, and puts the cache register in to data input mode. after the fifth address cycle is issued, the host must wait at least t ccs before inputting data. the selected lun stays in data-input mode until another va lid command is issued. though data-input mode is enabled, data input from the host is optional. data input begins at the column address specified. the change row address (85h) command is supported prior to the final command cycle (10h, 11h, 15h) of the following commands 1 : ? program page (80h-10h) ? program page multi-plane (80h-11h) ? program page cache (80h-15h) ? copyback program (85h-10h) ? copyback program multi-plane (85h-11h). notes: 1. when used with these commands, the lun address and plane-select bits must be identical to the lun address and plan e-select bits originally specified. the change row address (85h) command enables the host to modify the original page and block address for the data in the cache register to a new page and block address. the change row address (85h) command can be used with the change read column (05h-e0h) or change read column enhanced (06h-e0h) commands to read and modify cache register contents in small sections prior to programming cache register contents to the nand flash array. this capability can reduce the amount of buffer memory used in the host controller. to modify the cache register contents in small sections, first issue a page read (00h- 30h) or copyback read (00h-35h) operation. when data output is enabled, the host can output a portion of the cache register contents. to modify the cache register contents, issue the 85h command, the column and row addresses, and input the new cycle type i/o[7:0] (dq[7:0]) sr[6] command address address 85h c1 c2 t ccs d in dk d in dk + 1 d in dk + 2 d in dn d in dn + 1 as defined for page (cache) program as defined for page (cache) program
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 62 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance data. the host can re-enable data output by issuing the 11h command, waiting t dbsy, and then issuing the change read column (05h-e0h) or change read column enhanced (06h-e0h) command. it is possib le toggle between data output and data input multiple times. after the final change row address (85h) operation is complete, issue the 10h command to program the cache register to the nand flash array. in devices that have more than one lun per target, the change row address (85h) command can be used with other command s that support multi-lun operations. read operations read operations are used to copy data from the nand flash array of one or more of the planes to their respective cache registers, and to enable data output from the cache registers to the host through the dq bus. read operations the read page (00h-30h) command, when issued by itself, reads one page from the nand flash array to its cache register and en ables data output for that cache register. during data output the following commands can be used to read and modify the data in the cache registers: change read column (05h-e0h), change row address (85h). read multi-plane operations read multi-plane page operations improve data throughput by copying data from multiple planes to the specified cache registers simultaneously. this is done by prepending one or more read page multi-plane (00h-32h) commands in front of the read page (00h-30h) command. when the lun is ready, the select cach e register (06h-e0h) command determines which plane outputs data. during data outp ut the following commands can be used to read and modify the data in the cache re gisters: change read column (05h-e0h), change row address (85h). see ?multi-plane operations? on page 86 for details. read page cache operations for the highest sustainable level of data th roughput, the read page cache-series (31h, 00h-31h) commands can be used to output da ta from the cache register while concur- rently copying a page from the nand flash array to the data register. a read page cache command sequence is started when the read page (00h-30h) command is used to read a page from the nand flash array to its corresponding cache register. r/b# goes low during t r and the selected lun is busy (rdy = 0, ardy = 0). after t r (r/b# is high and rdy = 1, ardy = 1), either of the following commands can be issued: ? read page cache sequential (31h)?starts copying the next sequential page from the nand flash array to the data register. ? read page cache random (00h-31h)?starts copying the page specified in this command from the nand flash array (any pl ane) to its corresponding data register. after the read page cache-series (31h, 00h-31h) command has been issued, r/b# goes low on the target, rdy = 0 and ardy = 0 on the lun for t rcbsy, and the next page begins copying data from the array to the data register. after t rcbsy, r/b# goes high and the lun?s status register bits indicate th e device is busy with a cache operation (rdy
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 63 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance = 1, ardy = 0). the cache register become s available and the page requested in the read page cache operation is transferred to the data register. at this point, data can be output from the cache register, beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data output by the lun. after outputting the desired number of bytes from the cache register, either an addi- tional read page cache-series (31h, 00h- 31h) operation can be started or the read page cache last (3fh) command can be issued. if an additional read page cache-series (31h, 00h-31h) command is issued, r/b# goes low on the target, rdy = 0 and ardy = 0 on the lun for t rcbsy, the data register is copied to the cache register, then the next page begins copying into the data register. after t rcbsy, r/b# goes high, rdy = 1 and ardy = 0, indicating that the cache register is available for data output and that the specified page is copying from the nand flash array to the data register. data can then be output from the cache register, beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output by the cache register. if the read page cache last (3fh) command is issued, r/b# goes low on the target, rdy = 0 and ardy = 0 on the lun for t rcbsy, and the data register is copied into the cache register. after t rcbsy, r/b# goes high, rdy = 1 and ardy = 1, indicating that the cache register is available and that the lun is ready. data can then be output from the cache register, beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output. for read page cache-series (31h, 00h-31h, 3fh), during the lun busy time, t rcbsy, when rdy = 0 and ardy = 0, the only valid co mmands are status operations (70h, 78h) and reset (ffh, fch). when rdy = 1 and ardy = 0, the only valid commands during read page cache-series (31h, 00h-31h) operations are status operations (70h, 78h), read mode (00h), read page cache- series (31h, 00h-31h), change read column (05h-e0h), and reset (ffh, fch). page read multi-plane operat ions using cache operations page read multi-plane operations using cache improve data throughput by copying data from multiple planes to the sp ecified cache registers simultaneously then queuing additional planes to be read from the nand array while the pervious data read from the nand array is outputted. this is done by prepending read page multi- plane (00h-32h) commands in front of the page read cache random (00h-31h) command. when the lun is ready, the select cach e regsiter (06h-e0h) command determines which plane outputs data. during data outp ut the following commands can be used to read and modify the data in the cache re gisters: change read column (05h-e0h), change row address (85h). see ?multi-plane operations? on page 86 for additional multi-plane addressing require- ments. read mode (00h) the read mode (00h) command disables status output, and enables data output for the last-selected lun and cache register, afte r a read operation (00h-30h, 00h-35h) has been monitored with a status operation (70h , 78h). this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). it is also accepted by the lun during read page cache (31h, 3f, 00h-31h) operations (rdy = 1 and ardy = 0).
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 64 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance in devices that have more than one lun per target, during and following multi-lun operations, the select lun with status (78h) command must be used to select only one lun prior to issuing the read mode (00h) command. this prevents bus conten- tion. read page (00h?30h) the read page (00h?30h) command copies a page from the nand flash array to its respective cache register and enables data output. this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). a page from the nand flash array is read when the following sequence is performed: 1. the 00h command is written to the command register. 2. five address cycles are written to the address registers. 3. a read page (30h) command is issued. 4. the selected lun goes busy (rdy = 0, ardy = 0) for t r as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal, or alternatively, the status operations (70h, 78h) can be used. if the status opera- tions are used to monitor the lun's status, when the lun is ready (rdy = 1, ardy = 1), the host disables status output and enable s data output by issuing the read mode (00h) command. when the host requests data output, output begins at the column address specified. during data output the following commands can be used to read and modify the data in the cache registers: change read column (05h-e0h), change row address (85h). in devices that have more than one lun per target, during and following multi-lun operations the select lun with status (78h) command must be used to select only one lun prior to the issue of the read mode (00h) command. this prevents bus contention. the read page (00h-30h) command is used as the final command of a multi-plane read operation. it is preceded by one or more read page multi-plane (00h-32h) commands. data is transferred from the na nd flash array for all of the addressed planes to their respective cache registers. when the lun is ready (rdy = 1, ardy = 1), data output is enabled for the cache register linked to the plane addressed in the read page (00h-30h) command. when the host requests data output, output begins at the column address last specified in the re ad page (00h-30h) command. the select cache register (06h-e0h) command is used to enable data output in the other cache registers. see ?multi-plane addressing? on pa ge 86 for additional multi-plane addressing requirements. figure 41: read page (00h?30h) operation cycle type i/o[7:0] (dq[7:0]) rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 30h d out d n d out d n+1 d out d n+2
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 65 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance read page cache sequential (31h) the read page cache sequential (31h) command reads the next page in sequence within a block into the data register, while the previous page is output from the cache register. this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). it is also accepted by the lun during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). this command is issued when 31h is wr itten to the command register. after the command is issued, the following sequence occurs: 1. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t rcbsy. 2. r/b# goes high and the lun is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is avai lable and that the specified page is copying from the nand flash array to the data register. 3. data can be output from the cache register, beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output from the cache register. caution the read page cache sequential (31h) command can be used to cross block boundaries. if the read page cache sequential (31h) command is i ssued after the last pa ge of a block is read into the data register, the next page read will be the next logical block in the plane which the 31h command was i ssued. do no issu e the read page cache sequential (31h) command to cross lun boundaries. instead issue the read page cache last (3fh) command for the last page of a lun. in devices that have more than one lun per target, during and following multi-lun operations, this sequence is followed to select only one lun and prevent bus conten- tion: 1. the select lun with status (78h) command is issued. 2. the read mode (00h) command is issued. figure 42: read page cache sequential (31h) operation cycle type i/o[7:0] (dq[7:0]) rdy t wb t rcbsy t rr command d out d out d out command d out 31h rr t wb command 30h t wb t rcbsy t rr d0 dn 31h d0 command address x5 00h page address m page m page m+1 t r
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 66 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance read page cache random (00h?31h) the read page cache random (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). it is also accepted by the lun during read page cache (31h, 00h-31h) operations (rdy = 1, ardy = 0). this command is issued in the following sequence: 1. 00h is written to the command register. 2. five address cycles are written to the address register. 3. 31h is written to the command register. the lun address must match the same lun address as the previous read page (00h- 31h) command or, if applicable, the previo us read page cache random (00h-31h) command. there is no restriction on the plane address. after this command is issued, the following sequence occurs: 1. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t rcbsy. 2. r/b# goes high and the lun is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is avai lable and that the specified page is copying from the nand flash array to the data register. 3. data can be output from the cache register beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output from the cache register. in devices that have more than one lun per target, during and following multi-lun operations, this sequence is followed to select only one lun and prevent bus conten- tion: 1. the select lun with status (78h) command is issued. 2. the read mode (00h) command is issued. figure 43: read page cache random (00h?31h) operation cycle type dq[7:0] rdy t wb t rcbsy t rr command d out d out d out 31h rr t wb command 30h d0 dn command address x5 00h command 00h page address m address x5 page address n command 00h page m t r 1 cycle type i/o[7:0] (dq[7:0]) rdy d out command d out t wb t rcbsy t rr dn 31h d0 command 00h address x5 page address p page n 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 67 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance read page cache last (3fh) the read page cache last (3fh) command ends the read page cache sequence and copies a page from the data register to the cache register. this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). it is also accepted by the lun during read page cache (31h, 00h-31h) operations (rdy = 1, ardy = 0). this command is issued when 3fh is written to the command register. after the command is issued, the following sequence occurs: 1. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t rcbsy. 2. r/b# goes high and the lun is ready (rdy = 1, ardy = 1). 3. data can be output from the cache register beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output from the cache register. in devices that have more than one lun per target, during and following multi-lun operations, this sequence is followed to select only one lun and prevent bus conten- tion: 1. the select lun with status (78h) command is issued. 2. the read mode (00h) command is issued. figure 44: read page cache last (3fh) operation page read multi-plane (00h-32h) using cache the read page multi-plane (00h-32h) can be used to setup multi-plane cache read operations. the read page multi-plane (00h-32h) command queues a plane to transfer data from the nand flash array to its cache register. this command can be issued one or more times. each time a new pl ane address is specified, that pane is also queued for data transfer. the command is issu ed to select the final plane and to begin the read operation for all previously queued planes. this command is issued in the following sequence: 1. 00h is written to the command register. 2. five address cycles are written to the address register. 3. 32h is written to the command register. (t he column address in the address specified is ignored.) after this command is issued, the following sequence occurs: 1. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t dbsy. cycle type i/o[7:0] (dq[7:0]) rdy t wb t rcbsy rr command d out d out d out command d out d out d out 31h t wb t rcbsy t rr d0 d0 dn as defined for read page cache (sequential or random) dn 3fh page n page address n
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 68 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance note: during t dbsy, the only valid commands during read page multi-plane (00h-32h) are status operations (70h, 78h) and reset commands (ffh, fch). following t dbsy, to continue the multi-plane read operation, the only valid commands are status opera- tions (70h, 78h), read page multi-plane (00h-32h), and read page (00h-30h). 2. r/b# goes high and the lun is ready (rdy = 1, ardy = 1). 3. the lun and block are queued for data transfer from the array to the cache register for the addressed plane. note: additional read page multi-plane (00h -32h) commands can be issued to queue additional planes for data transfer. 4. the read page (00h-30h) command is issued. 5. data is transferred from the nand flash a rray for all of the addr essed planes to their respective cache registers. 6. when the lun is ready (rdy = 1, ardy = 1) , data output is enabled for the cache reg - ister linked to the even plane. 7. when the host requests data output, it be gins at the column address specified in the read page (00h-30h) command. note: to enable data output in the other cach e registers, the select cache register (06h-e0h) command can be issued. also, to change the column address within the currently selected plane, the change read column (05h-e0h) command can be issued. after the first sequence of read page mu lti-plane (00h-32h) and read page (00h- 30h) has been issued to the nand device addition cache read commands can be issued to the nand device. to begin cache read oper ations to other blocks before outputting data from the previous read operations, there are two options. the first option is to begin issuing the read page cache sequential (31h) command. issuing the read page cache sequential (31h) command will cause the next consecutive page within each block for ea ch plane that was addressed in steps 1 - 7 to be read. in the case issuing the read page cache sequential (31h) after the last page in a block has already been addressed, the first page in the next sequential block in that plane will be the next page read. the following shows this sequence: 8. the read page cache sequntial (31h) is issued. 9. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t rcbsy after r/b# goes high and the lun reports in the status register rdy = 1 and ardy = 0, that signals that the internal array read is ongoing and the cache register is ready to output data from the previous read operation. when a read page cache sequen- tial (31h) command is issued the column address defaults to 0. steps 8 and 9 can be repeated to continue reading consecutive pages. after issuing the last page address to be read, issue the read page cache last (3fh) to finish the cache reading operation. after r/b# goes high and the lun reports in the status register rdy = 1 and ardy = 0, that signals that the internal array read is ongoing and the cache register is ready to output data from the previous read operat ion. the select cache register (06h-e0h) command is required prior to outputting data. after the select cache register (06h-e0h) command is issued, the change read column (05h-e0h) command can also be issued.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 69 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance note: to enable data output in the other cache register or change the column address, the select cache register (06h-e0h) command can be issued. also, to change the column address within the currently select ed plane (after the select cache regis- ter (06h-e0h) command is issued), th e change read column (05h-e0h) com- mand can be issued. the second option is to issue the read page multi-plane (00h-32h) command followed by the read page cache random (00h-31h) command. by using read page multi-plane (00h-32h) command and the read page cache random (00h- 31h) random page addresses within the nand device can be selected instead of just the next sequential page address as with the read page cache sequential (31h) command. the column address with the read page multi-plane is ignored, data will come from byte 0 of subsequent pages read. the following shows this sequence: 1. the read page multi-plane (00h-32) is issued. the column address in the address specified is ignored. 2. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t dbsy. 3. the read page cache random (00h-31h) is issued. the column address in the address specified is ignored. 4. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t rcbsy. after r/b# goes high and the lun reports in the status register rdy = 1 and ardy = 0, that signals that the internal array read is ongoing and the cache register is ready to output data from the previous read operat ion. the select cache register (06h-e0h) command is required prior to outputting data. after the select cache register (06h-e0h) command is issued, the change read column (05h-e0h) command can also be issued. note: to enable data output in the other cache register or change the column address, the select cache register (06h-e0h) command can be issued. also, to change the column address within the currently select ed plane (after the select cache regis- ter (06h-e0h) command is issued), th e change read column (05h-e0h) com- mand can be issued. after issuing the last page address to be read, issue the read page cache last (3fh) to finish the cache reading operation. data output is similar to the previous cache read operations, requiring the select cache register (06h-e0h) command to be issued first. see ?multi-plane addressing? on page 86 for additional multi-plane addressing require- ments read page multi-plane (00h?32h) the read page multi-plane (00h-32h) comma nd queues a plane to transfer data from the nand flash array to its cache register. this command can be issued one or more times. each time a new plane address is specified, that plane is also queued for data transfer. the read page (00h-30h) command is issued to select the final plane and to begin the read operation for all previously queued planes. all queued planes will transfer data from the nand flash array to their cache registers. this command is issued in the following sequence: 1. 00h is written to the command register. 2. five address cycles are written to the address register.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 70 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance 3. 32h is written to the command register. (t he column address in the address specified is ignored.) after this command is issued, the following sequence occurs: 1. r/b# goes low and the lun is busy (rdy = 0, ardy = 0) for t dbsy. note: during t dbsy, the only valid commands are stat us operations (70h, 78h) and reset commands (ffh, fch). following t dbsy, to continue the multi-plane read operation, the only valid commands are status operat ions (70h, 78h), read page multi-plane (00h-32h), and read page (00h-30h). 2. r/b# goes high and the lun is ready (rdy = 1, ardy = 1). 3. the lun and block are queued for data transfer from the array to the cache register for the addressed plane. note: additional read page multi-plane (00h -32h) commands can be issued to queue additional planes for data transfer. 4. the read page (00h-30h) command is issued. 5. data is transferred from the nand flash a rray for all of the addr essed planes to their respective cache registers. 6. when the lun is ready (rdy = 1, ardy = 1) , data output is enabled for the cache reg - ister linked to the even plane. 7. when the host requests data output, it be gins at the column address specified in the read page (00h-30h) command. note: to enable data output in the other cach e registers, the select cache register (06h-e0h) command can be issued. also, to change the column address within the currently selected plane, the change read column (05h-e0h) command can be issued. see ?multi-plane addressing? on page 86 for additional multi-plane addressing require- ments. figure 45: read page multi-plane (00h?32h) operation cycle type i/o[7:0] (dq[7:0]) rdy command address address address address address command t wb t dbsy 00h c1 c2 command address address 00h c1 ... r1 r2 r3 32h
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 71 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance program operations within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (i.e. 0, 1, 2, ?.., 127). during a program operation, the contents of th e cache and/or data registers are modified by the internal control logic. program page operations the program page (80h-10h) command, when not preceded by the program page multi-plane (80h-11h) command, programs one page from the cache register to the nand flash array. when the lun is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that the operation has completed successfully. program page cache operations the program page cache (80h-15h) command can be used to improve program operation system performance. when this command is issued, the lun goes busy (rdy = 0, ardy = 0) while the cache register co ntents are copied to the data register, and the lun is busy with a program cache operation (rdy = 1, ardy = 0). while the contents of the data register are moved to the nand fl ash array, the cache regi ster is available for an additional program page cache (80h-15h) or program page (80h-10h) command. note: for program page cache-series (80h-15h) operations, during the lun busy times, t cbsy and t lprog, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h, 78h) and reset (ffh, fch). when rdy = 1 and ardy = 0, the only valid commands during program page cach e-series (80h-15h) operations are sta- tus operations (70h, 78h), program page cache (80h-15h), program page (80h- 10h), change write column (85h), ch ange row address (85h), and reset (ffh, fch). program page multi-plane program operations the program page multi-plane (80h-11h) command can be used to improve program operation system performance by en abling multiple pages to be moved from the cache registers to different planes of the nand flash array. this is done by prepending one or more program page mu lti-plane (80h-11h) commands in front of the program page (80h-10h) command. see ?multi-plane operations? on page 86 for details. program page multi-plane program cache operations the program page multi-plane (80h-11h) command can be used to improve program cache operation system performance by enabling multiple pages to be moved from the cache registers to the data register s and, while the pages are being transferred from the data registers to different planes of the nand flash array, free the cache regis- ters to receive data input from the host. this is done by prepending one or more program page multi-plane (80h-11h) commands in front of the program page cache (80h-15h) command. see ?multi-plane operations? on page 86 for details.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 72 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance program page (80h?10h) the program page (80h-10h) command enables the host to input data to a cache register, and moves the data from the cach e register to the specified block and page address in the array of the selected lun. this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). it is also accepted by the lun when it is busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). this command is issued in the following sequence: 1. 80h is written to the command register. note: unless this command has been preceded by a program page multi-plane (80h-11h) command, issuing 80h to the command register clears all of the cache reg- ister contents on the selected target. 2. a page is input to the cache register and moved to the nand flash array at the block and page address specified. 3. five address cycles containing the column address and row address are written to the address register. 4. the data input cycle begins. serial data is input, beginning at the specified column address. at any time during the data in put cycle, the change read column (05h) and change row address (85h) commands can be issued. 5. when the data input cycle has completed, 10h is written to the command register. 6. the selected lun goes busy (rdy = 0, ardy = 0) for t prog as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal or, alternatively, the status operatio ns (70h, 78h) may be used. when the lun is ready (rdy = 1, ardy = 1), the host sh ould check the status of the fail bit. in devices that have more than one lun per target, during and following multi-lun operations, the select lun with status (78h) command must be used to select only one lun for status output. use of the read status (70h) command could cause more than one lun to respond, resulting in bus contention. 7. if a multi-plane program operation is being performed, the program page (80h- 10h) command is written to the command r egister as the final command. it is pre - ceded by one or more program page multi-plane (80h-11h) commands. data is transferred from the cache registers for all of the addressed planes to the nand flash array. the host should check the status of the operation by using the status operations (70h, 78h). see ?multi-plane addressing? on page 86 for multi-plane addressing requirements. figure 46: program page (80h?10h) operation cycle type i/o[7:0] (dq[7:0]) rdy t adl command address address address address address 80h command 10h command 70h c1 c2 r1 r2 r3 d in d in d in d in d0 d1 dn d out status t wb t prog
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 73 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance program page cache (80h?15h) the program page cache (80h-15h) command enables the host to input data to a cache register; copies the data from the cach e register to the data register; then moves the data register contents to the specified block and page address in the array of the selected lun. after the data is copied to the data register, the cache register is available for additional program page cache (80h-15h) or program page (80h-10h) commands. the program page cache (80h-15h) command is accepted by the lun when it is ready (rdy = 1, ardy = 1). it is also accepted by the lun when busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). this command is issued in the following sequence to input a page to the cache register and move it to the nand array at the block and page address specified: 1. 80h is written to the command register. note: unless this command has been preceded by a program page multi-plane (80h-11h) command, issuing 80h to the command register clears all of the cache reg- ister?s contents on the selected target. 2. five address cycles containing the column address and row address are written [to the address register. 3. the data input cycles follow. serial data is input, beginning at the specified column address. at any time during the data in put cycle, the change read column (85h) and change row address (85h) commands can be issued. 4. when the data input cycle has completed, 15h is written to the command register. 5. the selected lun goes busy (rdy = 0, ardy = 0) for t cbsy to give the data register time to become available fr om a previous program cache operation; to copy data from the cache register to the data register; then begin moving the data register con - tents to the specified page and block address. to determine the progress of t cbsy, the host can monitor the target's r/b# signal or, alternatively, the status op erations (70h, 78h) can be used. when the lun?s status shows that it is busy with a program cache operation (rdy = 1, ardy = 0), the host should check the status of the failc bit to see if a previous cache operation was suc - cessful. 6. if, after t cbsy, the host wants to wait for the program cache operation to complete, without issuing the program page (80h-10h) command, the host should monitor ardy until it is ?1.? the host should then check the status of the fail and failc bits. in devices with more than one lun per target, during and following multi-lun oper - ations, the select lun with status (78h) command must be used to select only one lun for status output. use of the read status (70h) command could cause more than one lun to respond, resulting in bus contention. 7. the program page cache (80h-15h) comman d is used as the final command of a multi-plane program cache operation. it is preceded by one or more program page multi-plane (80h-11h) commands. data for all of the addressed planes is trans - ferred from the cache registers to the corresponding data registers, then moved to the nand flash array. the host should check th e status of the operation by using the sta - tus operations (70h, 78h). see ?multi-plane addressing? on page 86 for multi-plane addressing requirements.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 74 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance figure 47: program page cache (80h?15h) operation (start) figure 48: program page cache (80h?15h) operation (end) program page multi-plane 80h-11h the program page multi-plane (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the nand flash array. this comman d can be issued one or more times. each time a new plane address is specified that plan e is also queued for data transfer. to input data for the final plane and to begin the pr ogram operation for all previously queued cycle type i/o[7:0] (dq[7:0]) rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy cycle type i/o[7:0] (dq[7:0]) rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy cycle type i/o[7:0] (dq[7:0]) rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 15h 1 t wb t cbsy cycle type rdy t adl command address as defined for page cache program address address address address 80h c1 c2 r1 r2 r3 d in d in d in d in command d0 d1 dn 10h 1 t wb t lprog i/o[7:0] (dq[7:0])
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 75 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance planes, issue either the program page (80h-10h) command or the program page cache (80h-15h) command. all of the queued planes will move the data to the nand flash array. this command is accepted by the lun when it is ready (rdy = 1). to input a page to the cache register and qu eue it to be moved to the nand flash array at the block and page address specified, wr ite 80h to the command register. unless this command has been preceded by a program page multi-plane (80h-11h) command, issuing the 80h to the command regi ster clears all of the cache registers' contents on the selected target. write five address cycles containing the column address and row address; data input cycles follow. serial data is input beginning at the column address specified. at any time during the data input cycle, the change read column (85h) and change row address (85h) command s can be issued. when data input is complete, write 11h to the command register. the selected lun will go busy (rdy = 0 , ardy = 0) for t dbsy. to determine the progress of t dbsy, the host can monitor the target's r/b# signal, or alternatively, the status operations (70h, 78 h) can be used. when the lun's status shows that it is ready (rdy = 1), additional program page multi-plane (80h-11h) commands can be issued to queue additional planes for data transfer. alternatively, the program page (80h-10h) or program page cache (80h-15h) commands can be issued. when the program page (80h-10h) command is used as the final command of a multi-plane program operation, data is transf erred from the cache registers to the nand flash array for all of the addressed planes during t prog. when the lun is ready (rdy = 1, ardy = 1), the host should check the status of the fail bit for each of the planes to verify that programming completed successfully. when the program page cache (80h-15h) co mmand is used as the final command of a multi-plane program cache operation, da ta is transferred from the cache regis- ters to the data registers after the previous array operations finish. the data is then moved from the data registers to the nand flash array for all of the addressed planes. this occurs during t cbsy. after t cbsy, the host should check the status of the failc bit for each of the planes from the previous prog ram cache operation, if any, to verify that programming completed successfully. for the program page multi-plane (80h-11h), program page (80h-10h), and program page cache (80h-15h) commands, see ?multi-plane addressing? on page 86 for multi-plane addressing requirements. figure 49: program page multi-plane (80h?11h) operation cycle type i/o[7:0] (dq[7:0]) rdy t adl command address address address address address 80h c1 command address 80h ... c2 r1 r2 r3 d in d in d in command d0 dn 11h t wb t dbsy
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 76 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance erase operations erase operations are used to clear the contents of a block in the nand flash array to prepare its pages for program operations. erase operations the erase block (60h-d0h) command, when not preceded by the erase block multi-plane (60h-d1h) command, erases one block in the nand flash array. when the lun is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation completed successfully. multi-plane erase operations the erase block multi-plane (60h-d1h) co mmand can be used to improve erase operation system performance by enabling mu ltiple blocks to be erased in the nand flash array. this is done by prepending one or more erase block multi-plane (60h- d1h) commands in front of the erase block (60h-d0h) command. see ?multi-plane operations? on page 86 for details. erase block (60h?d0h) the erase block (60h-d0h) command erases the specified block in the nand flash array. this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). to erase a block, write 60h to the command register. then write three address cycles containing the row address; the page address is ignored. conclude by writing d0h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t bers while the block is erased. to determine the progress of an erase operatio n, the host can monitor the target's r/b# signal, or alternatively, the status operations (70h, 78h) can be used. when the lun is ready (rdy = 1, ardy = 1) the host should check the status of the fail bit. in devices that have more than one lun per target, during and following multi-lun operations, the select lun with status (78h) command must be used to select only one lun for status output. use of the read status (70h) command could cause more than one lun to respond, resulting in bus contention. the erase block (60h-d0h) command is us ed as the final command of a multi- plane erase operation. it is preceded by one or more erase block multi-plane (60h-d1h) commands. all of blocks in the ad dressed planes are erased. the host should check the status of the operation by using th e status operations (70h, 78h). see ?multi- plane addressing? on page 86 for multi-plane addressing requirements. figure 50: erase block (60h?d0h) operation cycle type i/o[7:0] (dq[7:0]) sr[6] command address address address command t wb t bers 60h r1 r2 r3 d0h
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 77 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance erase block multi-plane (60h?d1h) the erase block multi-plane (60h-d1h) command queues a block in the specified plane to be erased in the nand flash array. this command can be issued one or more times. each time a new plane address is specifie d, that plane is also queued for a block to be erased. to specify the final block to be erased and to begin the erase operation for all previously queued planes, issue the erase block (60h-d0h) command. this command is accepted by the lun when it is ready (rdy = 1, ardy = 1). to queue a block to be erased, write 60h to the command register, then write three address cycles containing th e row address; the page address is ignored. conclude by writing d1h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t dbsy. to determine the progress of t dbsy, the host can monitor the target's r/b# signal, or alternatively, the status operations (70h, 78 h) can be used. when the lun's status shows that it is ready (rdy = 1, ardy = 1), ad ditional erase block multi-plane (60h-d1h) commands can be issued to queue additional planes for erase. alternatively, the erase block (60h-d0h) command can be issued to erase all of the queued blocks. for the erase block multi-plane (60h-d1h) and erase block (60h-d0h) commands, see ?multi-plane addressing? on page 86 for multi-plane addressing requirements. figure 51: erase block multi-plane (60h?d1h) operation cycle type i/o[7:0] (dq[7:0]) rdy command address address address 60h command d1h r1 command address 60h ... r2 r3 t wb t dbsy
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 78 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance copyback operations copyback operations make it possible to transfer data within a plane from one page to another using the cache register. this is pa rticularly useful for block management and wear-leveling. the copyback operation is a two-step process consisting of a copyback read (00h- 35h) and a copyback program (85h-10h) command. to move data from one page to another on the same plane, first issue the copyback read (00h-35h) command. when the lun is ready (rdy = 1, ardy = 1), the host can transfer the data to a new page by issuing the copyback program (85h-10h) command. when the lun is again ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation completed successfully. to prevent bit errors from accumulating over multiple copyback operations, it is recommended that the host read the data ou t of the cache register after the copyback read (00h-35h) completes, prior to issuing the copyback program (85h-10h) command. the change read column (05h-e0h) command can be used to change the column address. the host should check the data for ecc errors and correct them. when the copyback program (85h-10h) command is issued, any corrected data can be input. the change write column (85h ) command can be used to change the column address. it is not possible to use the copyback operation to move data from one plane to another or from one lun to another. this is accomplished using a read page (00h- 30h) or copyback read (00h-35h) command, reading the data out of the nand, and then using a program page or copyback program (85h-10h) command with data input to program the data to a new plane or lun. between the copyback read (00h-35h) and copyback program (85h-10h) commands, the following commands are supported: status operations (70h, 78h), and column address operations (05h-e0h, 06h-e0h, 85h). reset operations (ffh, fch) can be issued after copyback read (00h-35h), bu t the contents of the cache registers on the target are not valid. in devices that have more than one lun pe r target, after copyback read (00h-35h) is issued, multi-lun operations are prohibit ed until after the copyback program (85h- 10h) command is issued. multi-plane copyback operations multi-plane copyback read operations improve read data throughput by copying data simultaneously from more than one plane to the specified cache registers. this is done by prepending one or more read page multi-plane (00h-32h) commands in front of the copyback read (00h-35h) command. the copyback program multi-plane (85h- 11h) command can be used to improve system performance of copyb ack program operations by enabling movement of multiple pages from the cache registers to different planes of the nand flash array. this is done by prepending one or more copyback program (85h-11h) commands in front of the copyback program (85h-10h) command. see ?multi-plane operations? on page 86 for details.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 79 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance copyback read (00h?35h) the copyback read (00h-35h) command is fu nctionally identical to the read page (00h-30h) command, except that 35h is written to the command register instead of 30h. see ?read page (00h?30h)? on page 64 for further details. though it is not required, it is recommended that the host read the data out of the device to verify the data prior to issuing the copyback program (85h-10h) command to prevent the propagation of data errors. figure 52: copyback read (00h?35h) operation figure 53: copyback read (00h?35h) with change read column (05h?e0h) operation copyback program (85h?10h) the copyback program (85h-10h) command is functionally identical to the program page (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. see ?program page (80h?10h)? on page 72 for further details. cycle type i/o[7:0] (dq[7:0]) rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 35h d out d n d out d n+1 d out d n+2 cycle type i/o[7:0] (dq[7:0]) rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 35h 1 cycle type i/o[7:0] (dq[7:0]) rdy command address address command t ccs 05h c1 c2 e0h d0 dk dj + n dk + 1 dk + 2 1 d out d out d out d out d out d out
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 80 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance figure 54: copyback program (85h?10h) operation figure 55: copyback program (85h?10h) wi th change write column (85h) operation copyback read multi-plane (00h-32h) the copyback read multi-plane (00h-32h) command is functionally identical to the read page multi-plane (00h-32h) command, except that the 35h command is written as the final command. the complete command sequence for the copyback read page mutli-plane is 00h-32h-00h- 35h. see "read page multi-plane (00h- 32h)" on page 66 for further details. copyback program multi-plane (85h-11h) the copyback program multi-plane (85h-11h ) command is functionally identical to the program page multi-plane (85h-11h ) command, except that when 85h is written to the command register, cache r egister contents are not cleared. see "program page multi-plane 80h-11h" on page 63 for further details. cycle type i/o[7:0] (dq[7:0]) rdy command address address address address address command t wb t prog 85h c1 c2 r1 r2 r3 10h cycle type i/o[7:0] (dq[7:0]) rdy command address address address address address t wb t prog 85h c1 c2 r1 r2 r3 1 cycle type i/o[7:0] (dq[7:0]) rdy command address address t ccs t adl 85h command 10h c1 c2 d in di dj d in d in di + 1 d in dj + 1 d in dj + 2 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 81 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance figure 56: copyback program multi-plane (85h?11h) operation cycle type i/o[7:0] (dq[7:0]) rdy t adl command address address address address address 85h c1 command address 85h ... c2 r1 r2 r3 d in d in d in command d0 dn 11h t wb t dbsy
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 82 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance one-time programmable (otp) operations this micron nand flash device offers a protected, one-time programmable nand flash memory area. thirty full pages (4,320 bytes per page) of otp data are available on the target, and the entire range is guaranteed to be good. customers can use the otp area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. in micron nand flash devices, the otp area leaves the factory in an erased state (all bits are "1"). programming enables the user to program only "0" bits in the otp area. the otp area cannot be erased, even if it is no t protected. protecting the otp area simply prevents further programming of the otp area. while the otp area is referred to as "o ne-time programmable," micron provides a unique way to program and verify data-befor e permanently protecting it and preventing future changes. the otp area is only accessible while in otp operation mode. to set the device to otp operation mode, issue the set features (efh) command to feature address 90h and write 01h to p1, followed by 3 cy cles of 00h to p2 through p4. when the device is in otp operation mode, all subsequent page read (00h-30h) and program page (80h-10h) commands are applied to the otp area. the otp area is assigned to page addresses 02h through 1fh. otp programming and protection are achieved in two discrete operations. each page in the otp area is programmed using the pr ogram otp page (80h-10h) command. the pages in the otp area (02h-1fh) must be programmed in ascending order. to protect the otp area, issue the 80h command followed by five address cycles (00h- 00h-01h-00h-00h), followed by the 10h command. r/b# goes low for t prog. to read pages in the otp area, whether or not the area is protected, issue the page read (00h-30h) command. erase commands are not valid while the device is in otp operation mode. to exit otp operation mode, issue the set features (efh) command to feature address 90h and write 00h to p1 through p4. if the host device issues a page progra m (80h-10h) command to an address beyond the maximum page-address range, the device will be busy for t obsy and the wp# status register bit will be"0," meaning that the page is write-protected. if the host device issues the page read (00h-30h) command to an address beyond the maximum page-address range, the data output will not be valid. to determine whether or not the device is busy during an otp operation, either monitor r/b# or use the read status (70h) command. use of the select lun with status (78h) command is prohibited while the otp operation is in progress. if the reset (ffh) command is issued while in otp operation mode, the device will exit otp operation mode and enter normal operatin g mode. if the device is in the synchro- nous interface it will exit otp operation an d enter normal operation mode in asynchro- nous interface. if the synchronous reset (fch) command is issued while in the otp operation mode, the device will exit otp operation mode and stay in synchronous interface.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 83 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance program otp page (80h?10h) the program otp page (80h-10h) command is used to write data to the pages within the otp area. an entire page is programmed at one time. to program data in the otp area, the device must be in otp operating mode. to use the program page command, issue the 80h command. issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles, select a page in the range of 02h-00h-00h through 1fh-00h-00h. next, write the data to the cache register using data input cycles. after data input is complete, issue the 10h command. r/b# goes low for the duration of the array programming time, t prog. the read status (70h) command is the only valid co mmand for reading status in otp operation mode. the rdy bit of the status register will reflect the state of r/b#. use of the select lun with status (78h) command is prohibited. when the device is ready, read the fail bit of the status register to determine if the oper- ation passed or failed (see table 14 on page 56). the program otp page (80h-10h) comma nd also accepts the change write column (85h) command during data input. if a program page command is issued to the otp area after the area has been protected, r/b# goes low for t obsy. after t obsy, the status register is set to 60h. it is possible to program each otp page a maximum of 8 times. figure 57: program otp page (80h?10h) operation cycle type i/o[7:0] (dq[7:0]) r/b# t adl t whr command address address address address address 80h command 70h command 10h c1 c2 otp page 00h 00h d out d in d in d in status d1 dn t wb t prog
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 84 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance figure 58: program otp page (80h?10h) with change write column (85h) operation protect otp area (80h?10h) to protect all data in the otp area, set the device to otp operating mode, then issue the protect otp area (80h-10h) command to page 1 in block 0 and write ?00h? for the first byte location. after the otp area is protected it cannot be programmed further. when the otp area is protected, the pages within the area are no longer programmable and cannot be unpro- tected. to use the protect otp area (80h-10h) co mmand to protect the otp area, issue the 80h command. next, issue the following 5 addr ess cycles: 00h-00h-01h-00h-00h. finally, issue the 10h command. r/b# goes low for the duration of the array programming time, t prog. the read status (70h) command is the only valid co mmand for reading status in otp operating mode. the rdy bit of the status register will reflect the state of r/b#. use of the select lun with status (78h) command is prohibited. if the protect otp area (80h-10h) command is issued after the otp area has already been protected, r/b# goes low for t obsy. after t obsy, the status register is set to 60h. when the device is ready, read the fail bit of the status register to determine if the oper- ation passed or failed (see table 14 on page 56). cycle type i/o[7:0] (dq[7:0]) r/b# t adl command address address address address address 80h c1 c2 otp page 00h 00h d in d in d in dn dm 1 cycle type i/o[7:0] (dq[7:0]) r/b# t whr command 70h command 10h command address address 85h c1 c2 d out status t ccs d in d in d in dp dr t wb t prog 1 command 85h
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 85 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory command definitions micron confidential and proprietary advance figure 59: protect otp area (80h?10h) operation notes: 1. otp data is protected following a "pass" status confirmation. read otp page (00h?30h) to read data from the otp area, set the device to otp operation mode, then issue the read otp page (00h-30h) command. data can be read from otp pages within the otp area whether or not the area is protected. to use the read otp page (00h-30h) command for reading data from the otp area, issue the 00h command. next, issue five address cycles: the first 2 address cycles are the column address, and for the remaining three cycles select a page in the range of 02h- 00h-00h through 1fh-00h-00h. finally, issue the 30h command. the selected lun will go busy (rdy = 0, ardy = 0) for t r as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal, or alternatively the read status (70h) command can be used. if the status oper- ations are used to monitor the lun's status, when the lun is ready (rdy = 1, ardy = 1) the host disables status output and enable s data output by issuing the read mode (00h) command. when the host requests data output, it begins at the column address specified. additional pages within the otp area can be selected by repeating the read otp page (00h-30h) command. the read otp page (00h-30h) command is compatible with the change read column (05h-e0h) command. use of the select lun with status (78h) and select cachr register (06h-e0h) commands are prohibited. figure 60: read otp page (00h?30h) operation cycle type i/o[7:0] (dq[7:0]) r/b# t adl t whr command address address address address address 80h command 70h command 10h 00h 00h 01h 00h 00h d out d in status 00h t wb t prog cycle type i/o[7:0] (dq[7:0]) r/b# command address address address address address command t wb t r t rr 00h c1 c2 otp page 00h 00h 30h d out d n d out d n+1 d out d n+2
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 86 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory multi-plane operations micron confidential and proprietary advance multi-plane operations each nand flash logical unit (lun) is divided into multiple physical planes. each plane contains a cache register and a data register independent of the other planes. the planes are addressed via the low-order block address bits. specific details are provided in figure 8 and table 2 on page 13. multi-plane operations make better use of the nand flash arrays on these physical planes by performing concurrent read, pr ogram, or erase operations on multiple planes, significantly improving system perfor mance. multi-plane operations must be of the same type across the planes; for example, it is not possible to perform a program operation on one plane with an erase operation on another. when issuing multi-plane program or erase operations, use the read status (70h) command and check whether the previo us operation(s) failed. if the read status (70h) command indicates that an error occurred (fail = 1 and/or failc = 1), use the select lun with status (78h) command?time for each plane?to deter- mine which plane operation failed. multi-plane addressing multi-plane commands require multiple 5-cyc le addresses, one address per operational plane. for a given multi-plane operation, th ese addresses are subject to the following requirements: ? the lun address bit(s) must be identi cal for all of the issued addresses. ? the plane select bit, ba[7], must be different for each issued address. ? the page address bits, pa[6:0], must be identical for each issued address. the read status (70h) command should be used following multi-plane program page and erase block oper ations on a single lun. multi-lun operations in devices that have more than one lun per target, it is possible to improve perfor- mance by interleaving operations between th e luns. a multi-lun operation is one that is issued to an idle lun (rdy = 1) while another lun is busy (rdy = 0). multi-lun operations are prohibited following reset (ffh, fch), identification (90h, ech, edh), and configuration (eeh, efh) operat ions until ardy =1 for all of the luns on the target. during a multi-lun operation, there are tw o methods to determine operation comple- tion. the r/b# signal indicates when all of the luns have finished their operations. r/b# remains low while any lun is busy. when r/b# goes high, all of the luns are idle and the operations are complete. alte rnatively, the select lun with status (78h) command can report the status of each lun individually. if a lun is performing a cache operation, like program page cache (80h-15h), then the lun is able to accept the data for anothe r cache operation when status register bit 6 is "1." all operations, including cache oper ations, are complete on a die when status register bit 5 is "1."
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 87 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory multi-lun operations micron confidential and proprietary advance during and following multi-lun operations, the read status (70h) command is prohibited. instead, use the select lun with status (78h) command to monitor status. this command selects which lun will report status. when multi-plane commands are used with multi-lun operatio ns, the multi-plane commands must also meet the requirements in ?multi-plane operations? on page 86. see table 5 on page 39 for the list of commands that can be issued while other luns are busy. during a multi-lun operation that involves a program-series (80h-10h, 80h-15h, 80h- 11h) operation and a read operation, the program-series operation must be issued before the read-series operation. the data from the read-series operation must be output to the host before the next program-series operation is issued. this is because the 80h command clears the cache register cont ents of all cache registers on all planes.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 88 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory error management micron confidential and proprietary advance error management each nand flash lun is specified to have a minimum number of va lid blocks (nvb) of the total available blocks. this means the luns could have blocks that are invalid when shipped from the factory. an invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ecc. additional blocks can develop with use. however, the total number of available blocks per lun will not fall below nvb during the endurance life of the product. although nand flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad-block management and error-correction algo- rithms. this type of software en vironment ensures data integrity. internal circuitry isolates ea ch block from other blocks, so the presence of a bad block does not affect the operation of the rest of the nand flash array. nand flash devices are shipped from the factory erased. the factory identifies invalid blocks before shipping by attempting to pr ogram the bad-block mark into every location in the first page of each invalid block. it may not be possible to program every location with the bad-block mark. however, the first spare area location in each bad block is guaranteed to contain the bad-block mark. this method is compliant with onfi factory defect mapping requirements. see table 15 for the first spare area location and the bad- block mark. system software should check the first spare ar ea location on the first page of each block prior to performing any program or erase operations on the nand flash device. a bad block table can then be created, enabling system software to map around these areas. factory testing is performed under wo rst-case conditions. because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, the following precautions are required: ? always check status after a program or erase operation. ? under typical conditions, use the minimum required ecc shown in table 15. ? use bad-block management an d wear-leveling algorithms. table 15: error management details description requirement minimum number of valid blocks (nvb) per lun 2,008 total available blocks per lun 2,048 first spare area location byte 4,096 bad-block mark 00h minimum required ecc 4-bit ecc per 540 bytes of data
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 89 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory output drive strength micron confidential and proprietary advance output drive strength because high speed nand flash is designed for use in systems that are typically point- to-point connections, an option to control th e drive strength of the output buffers is provided. drive strength should be selected based on the expected loading of the memory bus. there are four supported settings for the output drivers - overdrive 2, over- drive 1, nominal, and underdrive. the nominal output drive strength setting is the power-on default value. the host can select a different drive strength setting using the set features (efh) command. the output impedance range fr om minimum to maximum covers process, voltage, and temperature variations. devices are not gu aranteed to be at the nominal line. table 16: output drive strength test conditions (v cc q = 1.7?1.95v) range process voltage temperature minimum fast-fast 1.95v ?40c nominal typical-typical 1.8v +25c maximum slow-slow 1.7v +85c table 17: output drive strength impedance values (vccq = 1.7?1.95v) output strength rpd/rpu v out to v ss q maximum nominal minimum unit overdrive 2 rpd v cc q 0.2 7.5 13.5 34 ohms v cc q 0.5 9 18 31 ohms v cc q 0.8 11 23.5 44 ohms rpu v cc q 0.2 11 23.5 44 ohms v cc q 0.5 9 18 31 ohms v cc q 0.8 7.5 13.5 34 ohms overdrive 1 rpd v cc q 0.2 10.5 19 47 ohms v cc q 0.5132544ohms v cc q 0.8 16 32.5 61.5 ohms rpu v cc q 0.2 16 32.5 61.5 ohms v cc q 0.5132544ohms v cc q 0.8 10.5 19 47 ohms nominal rpd v cc q 0.2 15 27 66.5 ohms v cc q 0.5 18 35 62.5 ohms v cc q 0.8225288ohms rpu v cc q 0.2225288ohms v cc q 0.5 18 35 62.5 ohms v cc q 0.8 15 27 66.5 ohms underdrive rpd v cc q 0.2 21.5 39 95 ohms v cc q 0.5265090ohms v cc q 0.8 31.5 66.5 126.5 ohms rpu v cc q 0.2 31.5 66.5 126.5 ohms v cc q 0.5265090ohms v cc q 0.8 21.5 39 95 ohms
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 90 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory output drive strength micron confidential and proprietary advance notes: 1. mismatch is the absolute value between pull-up and pull-down impedances. both are mea - sured at the same temperature and voltage. 2. test conditions: vccq = vccq(min), vout = vccq 0.5. table 18: output drive strength conditions (vccq = 2.7-3.6v) range process voltage temperature minimum fast-fast 3.6v ?40c nominal typical-typical 3.3v +25c maximum slow-slow 2.7v +85c table 19: output drive strength impedance values (vccq = 2.7-3.6v) output strength rpd/rpu v out to vssq maximum nominal minimum unit overdrive 2 rpd vccq x 0.2 6.0 10.0 18.0 ohms vccq x 0.5 10.0 18.0 35.0 ohms vccq x 0.8 15.0 25.0 49.0 ohms rpu v cc q 0.2 15.0 25.0 49.0 ohms v cc q 0.5 10.0 18.0 35.0 ohms v cc q 0.8 6.0 10.0 18.0 ohms overdrive 1 rpd vccq x 0.2 8.0 15.0 30.0 ohms vccq x 0.5 15.0 25.0 45.0 ohms vccq x 0.8 20.0 35.0 65.0 ohms rpu v cc q 0.2 20.0 35.0 65.0 ohms v cc q 0.5 15.0 25.0 45.0 ohms v cc q 0.8 8.0 15.0 30.0 ohms nominal rpd vccq x 0.2 12.0 22.0 40.0 ohms vccq x 0.5 20.0 35.0 65.0 ohms vccq x 0.8 25.0 50.0 100.0 ohms rpu v cc q 0.2 25.0 50.0 100.0 ohms v cc q 0.5 20.0 35.0 65.0 ohms v cc q 0.8 12.0 22.0 40.0 ohms underdrive rpd vccq x 0.2 18.0 32.0 55.0 ohms vccq x 0.5 29.0 50.0 100.0 ohms vccq x 0.8 40.0 75.0 150.0 ohms rpu v cc q 0.2 40.0 75.0 150.0 ohms v cc q 0.5 29.0 50.0 100.0 ohms v cc q 0.8 18.0 32.0 100.0 ohms table 20: pull-up and pull-down output impedance mismatch drive strength minimum maximum notes overdrive 2 0 6.3 1, 2 overdrive 1 0 8.8 1, 2 nominal 0 12.3 1, 2 underdrive 0 17.5 1, 2
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 91 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory synchronous ac overshoot/ undershoot specifications micron confidential and proprietary advance synchronous ac overshoot/u ndershoot specifications the supported ac overshoot and undershoot ar ea depends on the timing mode selected by the host. figure 61: overshoot figure 62: undershoot table 21: overshoot / undershoot parameters parameter timing mode unit 0 (50ns) 1 (30ns) 2 (20ns) 3 (15ns) 4 (12ns) maximum peak amplitude provided for overshoot area 11111 v maximum peak amplitude provided for undershoot area 11111 v maximum overshoot are above v cc q 3 3 3 2.25 1.8 v-ns maximum undershoot area below v ss q 3 3 3 2.25 1.8 v-ns -aximumamplitude /vershootarea 4imens 6olts6 6 ## 1 5ndershootarea -aximumamplitude 4imens 6olts6 6 33 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 92 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory synchronous input slew rate micron confidential and proprietary advance synchronous input slew rate though all ac timing parameters are tested with a nominal input slew rate of 1v/ns, it is possible to run the device at a slower slew rate. the input slew rates shown below are sampled, and not 100 percent tested. if using slew rates slower than the minimum values, timing must be derated by the host. synchronous output slew rate the output slew rate is tested using the following setup with only one die per i/o channel. table 22: test conditions for input slew rate parameter value rising edge v il (dc) to v ih (ac) falling edge v ih (dc) to v il (ac) temperature range t a table 23: input slew rate (vccq = 1.7?1.95v) description timing mode unit 0 1 2 3 4 input slew rate (min) 0.5 0.5 0.5 0.5 0.5 v/ns derating factor for setup times tbd tbd tbd tbd tbd ps per 100mv derating factor for hold times tbd tbd tbd tbd tbd ps per 100mv table 24: test conditions for output slew rate parameter value rising edge v il (dc) to v ih (ac) falling edge v ih (dc) to v il (ac) output capacitive load (c load ) 5pf temperature range t a table 25: output slew rate (vccq = 1.7?1.95v) output drive strength min max unit overdrive 2 15.5v/ns overdrive 1 0.85 5 v/ns nominal 0.75 4 v/ns underdrive 0.6 4 v/ns
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 93 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance electrical characteristics stresses greater than those listed under "absolute maximum ratings" can cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods ca n affect reliability. notes: 1. voltage on any pin relative to v ss . notes: 1. all values are per lun unless otherwise specified. table 26: absolute maximum ratings by device parameter symbol min 1 max 1 unit voltage input v in -0.6 4.6 v v cc supply voltage v cc -0.6 4.6 v v cc q supply voltage v cc q-0.64.6v storage temperature t stg -65 150 c table 27: recommended operating conditions parameter symbol min typ max unit operating temperature commercial t a 0?70c industrial ?40 ? +85 v cc supply voltage v cc 2.7 3.3 3.6 v v cc q supply voltage (1.8v) v cc q1.7 1.81.95 v vccq supply voltage (3.3v) 2.7 3.3 3.6 v v ss ground voltage v ss 000v table 28: asynchronous device dc and operating characteristics parameter conditions symbol min 1 typ 1 max 1 unit array read current ?i cc 1_a ? 20 50 ma array program current ?i cc 2_a ? 20 50 ma array erase current ?i cc 3_a ? 20 50 ma i/o burst read current t rc = t rc (min); iout = 0ma icc4r_a ? tbd tbd ma i/o burst write current t wc = t wc (min) icc4w_a ? tbd tbd ma bus idle current ? icc5_a ? tbd tbd ma standby current (cmos) ce# = v cc q - 0.2v; wp# = 0v/v cc i sb _a ? 10 50 a
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 94 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. all values are per lun unless otherwise specified. table 30: ball capacitance: bga-100 package notes: 1. verified in device charac terization; not 100 percent tested. 2. test conditions: ta = 25oc, f = 100mhz, vin = 0v. 3. values for c ck , c in and c io (typ) are estimates. 4. sdp = single die pacakge. table 31: pin capacitance: tsop-48 package notes: 1. these parameters are verified in device ch aracterization and are no t 100 percent tested.test conditions: t c = 25c; f = 1 mhz; v in = 0v. 2. sdp = single die package.. table 29: synchronous device dc and operating characteristics parameter conditions symbol min 1 typ 1 max 1 unit array read current t ck = t ck (min) i cc 1_s ? 20 50 ma array program current t ck = t ck (min) i cc 2_s ? 20 50 ma array erase current t ck = t ck (min) i cc 3_s ? 20 50 ma i/o burst read current t ck = t ck (min); iout = 0ma icc4r_s ? tbd tbd ma i/o burst write current t ck = t ck (min) icc4w_s ? tbd tbd ma bus idle current t ck = t ck (min) icc5_s ? tbd tbd ma standby current (cmos) ce# = v cc q - 0.2v; wp# = 0v/v cc i sb _s ? 10 50 a description symbol sdp 4 unit notes min typ max input capacitance (clk) c ck 3.35 3.6 3.85 pf 1, 2, 3 input capacitance (ale, cle, w/r#) c in 3.5 4 4.5 pf 1, 2, 3 input/output capacitance (dq[7:0], dqs) c io 4 4.5 5 pf 1, 2, 3 input capacitance (ce#, wp#) c other ? ? 5 pf 1, 2 delta clock capacitance dc ck ? ? 0.25 pf 1, 2 delta input capacitance dc in ? ? 0.5 pf 1, 2 delta input/output capacitance dc io ? ? 0.5 pf 1, 2 description symbol device 2 max unit notes input/output capacitance ale, ce#, cle, r/b#, re#, we#, wp# cin/cout sdp 10 pf 1 input/output capacitance (i/o[7:0], dq[7:0]) cin/cout sdp 5 pf 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 95 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance table 32: pad capacitance: lga-52 package notes: 1. these parameters are verified in device characterization and are not 100 percent tested. test conditions: t c = 25c; f = 1 mhz; v in = 0v. 2. sdp = single die package. notes: 1. transmission line delay is assumed to be very small. 2. this test setup applies to all package configurations. description symbol device 2 max unit notes input/output capacitance ale, ce#, cle, r/b#, re#, we#, wp# cin/cout sdp 10 pf 1 input/output capacitance i/o[7:0] cin/cout sdp 5 pf 1 table 33: test conditions parameter value notes input pulse levels 0v to v cc q? input rise and fall slew rates 1v/ns ? input and output timing levels v cc q/2 ? output load: synchronous interface, nominal output drive strength c l = 5pf 1, 2 output load: asynchronous interface, nominal output drive strength (vccq = 1.7 ? 1.95v) c l = 30pf 2 output load: asynchronous interface, nominal output drive strength (vccq = 2.7 ? 3.6v) c l = 50pf 2
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 96 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. all leakage currents are per lun. 2. dc characteristics may need to be relaxed if r/b# pull-down strength is not set to ?full.? see table 13 on page 14 for additional details. table 34: 3.3v vccq device operating characteristics parameter condition symbol min typ max unit notes ac input high voltage ce#, dq[7:0], dqs, dqs#, ale, cle, clk (we#), clk#, w/r# (re#), wp# vih (ac) 0.8 vccq ? vccq + 0.3 v ? ac input low voltage vil (ac) ?0.3 ? 0.2 vccq v ? output high voltage ioh = ?400a voh 0.67 vccq ??v? output low voltage iol = 2.1ma vol ? ? 0.4 v ? input leakage current any input vin = 0v to vccq (all other pins under test=0v) ili ? ? 10 a 1 output leakage current i/os are disabled; vout = 0v to vccq ilo ? ? 10 a 1 output low current (r/b#) vol = 0.4v iol (r/b#) 8 10 ? ma 2
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 97 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. the dc values only appl y to the synchronous interface. 2. v oh and v ol only apply to the asynchronous interface. 3. all leakage currents are per lun. table 35: 1.8v vccq device operating characteristics parameter condition symbol min typ max unit notes ac input high voltage ce#, dq[7:0], dqs, ale, cle, clk (we#), w/r# (r/e#), wp# v ih (ac) 0.8 v cc q ?v cc q + 0.3 v? ac input low voltage v il (ac) -0.3 ? 0.2 v cc q v? dc input high voltage dq[7:0], dqs, ale, cle, clk (we#), w/r# (r/e#) v ih (dc) 0.7 v cc q ?v cc q + 0.3 v1 dc input low voltage v il (dc) -0.3 ? 0.3 v cc q v1 output high voltage i oh = -100a v oh v cc q - 0.1 ? ? v 2 output low voltage i ol = -100a v ol ??0.1v2 input leakage current any input v in = 0v to v cc q (all other pins under test = 0v) i li ??10a3 output leakage current i/os are disabled; v out = 0v to v cc q i lo ??10a3 output low current (r/b#) v ol = 0.2v i ol (r/b#) 3 4 ? ma ?
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 98 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance table 36: ac characteristic: synchro nous command, address, and data parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 unit notes min max min max min max min max min max clock period 50 30 20 15 12 ns ? frequency 20 33506783 mhz ? access window of dq[7:0] from clk t ac ?20?20?20?20?20 ns ? ale to data loading time t adl 100 ? 100 ? 70 ? 70 ? 70 ? ns ? cmd, addr, data delay t cad 25?25?25?25?25? ns 1 ale, cle, w/r# hold t calh 10?5?4?3?2.5? ns ? ale, cle, w/r# setup t cals 10?5?4?3?2.5? ns ? dq hold - cmd, addr t cah 10?5?4?3?2.5? ns ? dq setup - cmd, addr t cas 10?5?4?3?2.5? ns ? change column setup to data in/out or next command t ccs 200 ? 200 ? 200 ? 200 ? 200 ? ns 2 ce# hold t ch 10?5?4?3?2.52 ns ? average clk cycle time t ck (avg) 501003050203015201215 ns 3 absolute clk cycle time, from rising edge rising edge t ck (abs) t ck (abs) min = t ck (avg) + t jit(per) min t ck (abs) max = t ck (avg) + t jit(per) max ns clk cycle high t ckh (abs) 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 t ck 4 clk cycle low t ckl (abs) 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 t ck 4 data output end to w/r# high t ckwr t ckwr(min) = roundup[ t dqsck(max) + t ck) / t ck] t ckwr(max): - t ck ? ce# setup t cs 35?25?15?15?15? ns ? data in hold t dh 5 ? 2.5 ? 1.7 ? 1.3 ? 1.1 ? ns ? access window of dqs from clk t dqsck ?20?20?20?20?20 ns ? dqs, dq[7:0] driven by nand t dqsd 020020020020020 ns ? dqs, dq[7:0] to tri-state t dqshz ?20?20?20?20?20 ns 5 dqs input high pulse width t dqsh 0.40.60.40.60.40.60.40.60.40.6 t ck ? dqs input low pulse width t dqsl 0.40.60.40.60.40.60.40.60.40.6 t ck ? dqs-dq skew t dqsq ? 5 ?2.5?1.7?1.3?1.1 ns ? data input t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck ? data in setup t ds 5?3?2?1.5?1.1? ns ?
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 99 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. delay is from start of command to next co mmand, address, or data cycle; start of address to next command, address, or data cycle; and end of data to start of next command, address, or data cycle. 2. this value is specifie d in the parameter page. 3. t ck(avg) is the average clock period ov er any consecutive 200-cycle window. 4. t ckh(abs) and t ckl(abs) include static of fset and duty cycle jitter. 5. t dqshz begins when w/r# is latched high by clk. this parameter is not referenced to a specific voltage level; it specifies when the device outputs are no longer driving. 6. if reset (ffh) is issued when the target is idle, the target goes bu sy for a maximum of 5s. dqs falling edge from clk rising - hold t dsh 0.2 ? 0.2 ? 0.2 ? 0.2 ? 0.2 ? t ck ? dqs falling to clk rising - setup t dss 0.2 ? 0.2 ? 0.2 ? 0.2 ? 0.2 ? t ck ? data valid window t dvw t dvw = t oh - t dqsq ns ? half clock period t hp t hp = min( t ckh, t ckl) ns ? the deviation of a given t ck(abs) from t ck(avg) t jit(per) -0.7 0.7 -0.7 0.7 -0.7 0.7 -0.6 0.6 -0.6 0.6 ns dq-dqs hold, dqs to first dq to go non- valid, per access t qh t qh = t hp - t qhs ns ? data hold skew factor t qhs ?6?3?2?1.5?1.2ns ? data output to command, address, or data input t rhw 100 ? 100 ? 100 ? 100 ? 100 ? ns ? ready to data output t rr 20?20?20?20?20? ns ? device reset time (read/program/erase) t rst ?5/10/ 500 ?5/10/ 500 ?5/10/ 500 ? 5/10/ 500 ?5/10/ 500 s 6 clk high to r/b# low t wb ? 100 ? 100 ? 100 ? 100 ? 100 ns ? command cycle to data output t whr 80?60?60?60?60? ns ? dqs write preamble t wpre 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? t ck ? dqs write postamble t wpst 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? t ck ? w/r# low to data output cycle t wrck 20?20?20?20?20? ns ? wp# transition to command cycle t ww 100 ? 100 ? 100 ? 100 ? 100 ? ns ? table 37: ac characteristics: asynchronous command, address, and data parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 unit notes min max min max min max min max min max clock period 10050353025ns table 36: ac characteristic: synchronous command, address, and data (continued) parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 unit notes min max min max min max min max min max
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 100 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance frequency 10 2 0 2 8 33 40 mhz ale to data start t adl 200 ? 100 ? 100 ? 100 ? 70 ? ns 1 ale hold time t alh 20 ? 10 ? 10 ? 5 ? 5 ? ns ale setup time t als 50 ? 25 ? 15 ? 10 ? 10 ? ns ale to re# delay t ar 25 ? 10 ? 10 ? 10 ? 10 ? ns ce# access time t cea ?100?45?30?25?25 ns change column setup to data in/out or next command t ccs 200 ? 200 ? 200 ? 200 ? 200 ? ns ce# hold time t ch 20 ? 10 ? 10 ? 5 ? 5 ? ns ce# high to output high-z t chz ?100?50?50?50?30 ns 2 cle hold time t clh 20 ? 10 ? 10 ? 5 ? 5 ? ns cle to re# delay t clr 20 ? 10 ? 10 ? 10 ? 10 ? ns cle setup time t cls 50 ? 25 ? 15 ? 10 ? 10 ? ns ce# high to output hold t coh 0 ?15?15?15?15? ns ce# setup time t cs 70 ? 35 ? 25 ? 25 ? 20 ? ns data hold time t dh 20 ? 10 ? 5 ? 5 ? 5 ? ns data setup time t ds 40 ? 20 ? 15 ? 10 ? 10 ? ns output high-z to re# low t ir 10 ? 0 ? 0 ? 0 ? 0 ? ns re# cycle time t rc 100 ? 50 ? 35 ? 30 ? 25 ? ns re# access time t rea ?40?30?25?20?20 ns 3 re# high hold time t reh 30 ? 15 ? 15 ? 10 ? 10 ? ns 3 re# high to output hold t rhoh 0 ?15?15?15?15? ns 3 re# high to we# low t rhw 200 ? 100 ? 100 ? 100 ? 100 ? ns re# high to output high-z t rhz ? 200 ? 100 ? 100 ? 100 ? 100 ns 2, 3 re# low to output hold t rloh 0?0?0?0?5? ns 3 re# pulse width t rp 50 ? 25 ? 17 ? 15 ? 12 ? ns ready to re# low t rr 40 ? 20 ? 20 ? 20 ? 20 ? ns device reset time (read/program/erase) t rst ? 5/10/ 500 ? 5/10/ 500 ? 5/10/ 500 ? 5/10/ 500 ? 5/10/ 500 s 4, 5 we# high to r/b# low t wb ? 200 ? 100 ? 100 ? 100 ? 100 ns 6 we# cycle time t wc 100 ? 45 ? 35 ? 30 ? 25 ? ns we# high hold time t wh 30 ? 15 ? 15 ? 10 ? 10 ? ns we# high to re# low t whr 120 ? 80 ? 80 ? 60 ? 60 ? ns we# pulse width t wp 50 ? 25 ? 17 ? 15 ? 12 ? ns table 37: ac characteristics: asynchronous command, address, and data (continued) parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 unit notes min max min max min max min max min max
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 101 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. timing for t adl begins in the address cycle, on the fi nal rising edge of we# and ends with the first rising edge of we# for data input. 2. data transition is measured 200mv from ste ady-steady voltage with load. this parameter is sampled and not 100 percent tested. 3. ac characteristics may need to be relaxed if ou tput drive strength is not set to at least nom - inal. 4. if reset (ffh) command is issu ed when the target is ready, the target goes busy for a max - imum of 5s. 5. see table 39 for details on the power-on reset time, t por 6. do not issue a ne w command during t wb, even if r/b# or rdy is ready. notes: 1. invalid blocks are block that contain one or more bad bits beyond ecc. the device may con - tain bad blocks upon shipment. additional ba d blocks may develop over time; however, the total number of available blocks will not drop below nvb during the endurance life of the device. do not erase or program bloc ks marked invalid from the factory. notes: 1. the pages in the otp block have an nop of 8. 2. t itc (max) is the busy time when the interfa ce changes from asynchro nous to synchronous using the set features (efh) command or synchronous to asynchronous using the reset (ffh) command. during the t itc time, any command, incl uding read status (70h) and select lun with status (78h), is prohibited. 3. t lprog = t prog (last page) + t prog (last page - 1) - comm and load time (last page) - address load time (last page) - data load time (last page). wp# transition to we# low t ww 100 ? 100 ? 100 ? 100 ? 100 ? ns table 38: valid blocks per lun parameter symbol min max unit notes valid block number n vb 2,008 2,048 blocks 1 table 39: array characteristics parameter symbol typ max unit notes number of partial page programs nop ?4cycles1 erase block operation time t bers 0.7 3 ms cache busy t cbsy 3500s dummy busy time t dbsy 0.5 1 s cache read busy time t rcbsy 325s busy time for set features and get features operations t feat ?1s busy time for interface change t itc ?1s2 last page program operation time t lprog ??s3 busy time for otp data program operation if otp is protected t obsy ?30s power-on reset time t por ?1ms program page operation time t prog 200 500 s read page operation time t r ?25s table 37: ac characteristics: asynchronous command, address, and data (continued) parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 unit notes min max min max min max min max min max
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 102 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance timing diagrams synchronous interface notes: 1. when ce# remains low, t cad begins at the rising edge of the clock from which the last data byte is input for the subseque nt command or data input cycle(s). 2. t dsh (min) generally occurs during t dqss (min). 3. t dss (min) generally occurs during t dqss (max). 4. the cycle that tcad is measured from may be an idle cycle (as sh own), another command cycle, and address cycle, or a data cycle. the id le cycle is shown in this diagram for simplicity. clk ce# ale cle w/r# r/b# dqx t cad efh feat addr feat addr t feat t wb dont care t cad t cs t cad p1 0 p1 1 p2 0 p2 1 p3 0 p3 1 p4 0 p4 1 dqs t cals t cals t dqss
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 103 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 63: read id operation clk ce# ale cle w/r# dqx 90h 00h or 20h t dqsd dont care t cad t cs t cad t dqshz dqs t rhw t cals t dqsck t cals driven t calh t ckwr t calh t whr byte 0 byte 0 byte 1 byte 2 byte 3 byte 3 byte 4 byte 4 byte 2 byte 1 t cals
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 104 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 64: get features operation clk ce# ale cle w/r# r/b# dqx eeh t feat t dqsd t wb dont care t cad t cs t cad t dqshz dqs t rhw t cals t dqsck driven t calh t ckwr t calh t wrck feat addr p1 p2 p3 p4 t cals t cals t cals
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 105 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 65: read status cycle clk ce# ale cle w/r# r/b# dqx read status command 70h t whr dont care dqs t dqsd t rhw t cad t ckwr t dqshz driven status status
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 106 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 66: select lun with status operation clk ce# ale cle w/r# dqx 78h t whr dont care t cad t cs t cad t cad t cad dqs t dqsd t rhw t cad t ckwr t dqshz driven row add 1 row add 2 row add 3 status status
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 107 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 67: read parameter page operation clk ce# ale cle w/r# r/b# dqx ech t r t dqsd t wb dont care t cad t cs t cad t dqshz dqs t rhw t dqsck t cals driven t calh t ckwr t calh t wrck 00h p1 p2 pn-3 pn-2 pn-1 pn p0 t cals t cals
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 108 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 68: read page operation clk ce# ale cle w/r# r/b# dqx t cad 00h col add 1 col add 2 t r t wb dont care t cad t cs t cad t cad t cad t cad t cad dqs 30h row add 1 row add 2 row add 3 t cals driven clk ce# ale cle w/r# r/b# dqx t cad *x8 device: m = 4,320 bytes 1 up to m byte serial input* t r t dqsd t wb t cad t dqshz dqs 30h t rhw t cals t cals t dqsck row add 3 t cals t cals t calh t ckwr t calh t wrck dout 0 dout n-3 dout n-2 dout n-1 dout n 1 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 109 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 69: change read column clk ce# ale cle w/r# r/b# dqx dont care t cad t cad t cad dqs 05h col add 1 col add 2 e0h t dqsd d out c+1 d out d-2 d out c d out d-1 d out d t dqshz t rhw t dqsck t cals t ccs t rhw driven t cals
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 110 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 70: read page cache sequential (1 of 2) clk ce# ale cle w/r# r/b# dqx t r t dqsd t wb dont care t dqshz dqs 30h t rhw t dqsck 31h t rcbsy t wb t wb 31h t rcbsy data output t dqsd driven initial read access sequential read access a sequential read access b initial read data 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 111 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 71: read page cache sequential (2 of 2) clk ce# ale cle w/r# r/b# dqx dont care dqs t rcbsy t wb t rcbsy t dqsd t dqshz t rhw t dqsck data output 3fh t dqsd t dqshz t rhw t dqsck data output driven sequential read data a sequential read data b 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 112 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 72: read page cache random (1 of 2) clk ce# ale cle w/r# r/b# dqx t r t dqsd t wb t dqshz dqs 30h t rhw t dqsck t rcbsy t wb t cad x 4 00h t wb t cad 31h t rcbsy 5 address cycles data output dont care driven t rhw t cad x 4 00h t cad 31h 5 address cycles initial read access random read access a random read access b initial read data 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 113 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 73: read page cache random (2 of 2) clk ce# ale cle w/r# r/b# dqx dont care dqs t cad x 4 t wb 31h t rcbsy t wb t rcbsy t dqsd t dqshz t rhw t dqsck data output 3fh t dqsd t dqshz t rhw t dqsck data output driven random read access b random read data a random read data b 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 114 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 74: multi-plane read page (1 of 2) clk w/r# ce# ale cle rdy dqx dqs t wb t dbsy 32h or 00h t cad x 5 t cad address a 5 cycles 00h t wb t r t dqsd 06h t cals 00h t cad address b 5 cycles t cad x 5 30h t dqsck t rhw data a output t dqshz if data from a plane other than a is desired, a 06h-e0h command sequence is required after t r and prior to taking w/r# low. 1 t cals dont
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 115 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 75: multi-plane read page (2 of 2) w/r# w/r# 2 3 clk ce# ale cle rdy dqx dqs e0h t dqsd t dqshz t dqsck data b output 06h t cad address a 5 cycles t rhw t cad x 5 e0h t dqsd t dqsck 3 clk ce# ale cle rdy dqx dqs t dqshz t dqsck data a output 06h t cad address b 5 cycles t rhw t cad x 5 e0h t dqsd t dqshz t dqsck data b output t rhw dont care undefined (driven by nand) t ccs t ccs
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 116 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 76: program page operation (1 of 2) clk ce# ale cle w/r# r/b# dqx t adl 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n+1 d in m-2 t cad t cs t cad t cad t cad t cad t cad d in n d in m-1 d in m dqs t cals t cals t dqss dont care driven 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 117 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 77: program page operation (2 of 2) dont care driven clk ce# ale cle w/r# r/b# dqx read status command d in n+1 d in m-2 70h 10h t prog t whr t wb d in n d in m-1 d in m t cad dqs t cals t dqss t dqsd t rhw t cad t ckwr t dqshz status status 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 118 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 78: change write column clk ce# ale cle w/r# r/b# dqx t ccs 85h col add 1 col add 2 d in c+1 t cad t cad t cad d in c dqs t dqss d in n+1 d in m-2 d in m-1 d in m t cals dont care driven t cals 1 clk ce# ale cle w/r# r/b# dqx t ccs 85h col add 1 col add 2 d in c+1 d in d-2 t cad t cad t cad d in c d in d-1 d in d dqs t dqss t cad t cals t cals 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 119 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 79: multi-plane program page clk ce# ale cle w /r# rdy dqx dqs 80h t cad t cad t cad x 4 + t adl address a 5 cycles t dqss 11h t cad data a t cals t cals t dbsy t wb 80h t cad clk ce# ale cle w/r# rdy dqx dqs t cad x 4 + t adl t dqss 1 1 address b 5 cycles 70h 10h t prog t whr t wb t cad t dqsd t cad t rhw t dqshz status status data b address b 5 cycles
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 120 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 80: erase block clk ce# ale cle w/r# r/b# dqx t cad 60h t bers t wb dont care t cad t cs t cad t cad t cad dqs d0h row add 1 row add 2 row add 3 read status command 70h t whr status status t dqsd t dqshz t rhw t cad driven
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 121 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 81: copyback (1 of 3) clk ce# ale cle w/r# r/b# dqx dqs t cad x 5 00h t wb t cad 35h or 30h t r 5 address cycles t dqsd t dqshz t dqsck data output 05h t cad t cadx2 e0h 2 address cycles t rhw 1 dont care driven
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 122 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 82: copyback (2 of 3) clk ce# ale cle w/r# r/b# dqx dqs h t dqsd data output t dqsck t rhw t dqshz t cad x 5 85h t cad 5 address cycles 85h t cad t cad + t adl 2 address cycles data t cals t cals t dqss 1 2 dont care driven
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 123 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 83: copyback (3 of 3) clk ce# ale cle w/r# r/b# dqx dqs 70h 10h t prog t whr t wb dont care t cad status status t dqsd t dqshz t cad t rhw driven 2
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 124 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 84: read otp page clk ce# ale cle w/r# r/b# dqx t cad 00h col add 1 col add 2 t r t dqsd t wb dont care t cad t cs t cad t cad t cad t cad t cad d out 0 d out n t dqshz dqs 30h t rhw t cals t cals t dqsck t cals t cals d out n-1 driven d out n-2 d out n-3 t calh t ckwr t calh 00h 00h otp page 1 t wrck
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 125 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 85: program otp page (1 of 2) clk ce# ale cle w/r# r/b# dqx t adl 80h col add 1 col add 2 d in n+1 d in m-2 dont care t cad t cs t cad t cad t cad t cad t cad d in n d in m-1 d in m dqs t cals t cals t dqss 00h 00h otp page 1 driven 1
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 126 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 86: program otp page (2 of 2) dont care driven transitioning clk ce# ale cle w/r# r/b# dqx read status command d in m-2 70h 10h t prog t whr t wb d in m-1 d in m t cad dqs t cals t dqsd t rhw t cad t ckwr otp data written (following "pass" status confirmation) t dqshz 1 status status
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 127 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 87: protect otp area clk ce# ale cle w/r# r/b# dqx 80h col 00h col 00h 00h t dqss t cad t cad t cad t cad t cad t cad t adl dqs 00h 01h 00h dont care driven transitioning clk ce# ale cle w/r# r/b# dqx read status command 70h 10h t prog t whr t wb t cals t cad dqs t dqsd t dqshz t rhw t cad status status 1 1 t cals
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 128 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance asynchronous interface figure 88: reset operation figure 89: read status cycle cle ce# we# r/b# i/ox (dqx) t rst t wb ffh reset command re# ce# we# cle i/ox (dqx) t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h status output dont care t cea t coh
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 129 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 90: select lun with status cycle figure 91: read parameter page t whr t ar dont care 78h row add 1 row add 2 row add 3 status output t ds t dh t wp t wp t wc t ch t als t alh t wh t cls t clh t alh t cs t cea t chz t rea t rhoh t rhz t coh i/ox (dqx) re# ale we# cle ce# we# ale cle re# r/b# ech 00h t r p0 0 p1 0 p255 0 p0 1 t wb t rr i/ox (dqx) t rp t rc
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 130 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 92: read page d out n d out n + 1 d out m we# ce# ale cle re# rdy i/ox (dqx) t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz dont care col add 1 col add 2 row add 1 row add 2 row add 3
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 131 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 93: read page operation with ce# ?don?t care? figure 94: change read column re# ce# t rea t chz t coh t cea re# ce# ale cle i/ox (dqx) i/ox out rdy we# data output t r dont care address (5 cycles) 00h 30h we# ce# ale cle re# rdy i/ox (dqx) t rhw t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n C 1 d out n t ccs column address m
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 132 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 95: read page cache sequential t wc we# ce# ale cle re# r/b# i/ox column address 0 page address m page address m column address 00h t cea t ds t clh t cls t cs t ch t dh t rr t wb t r t rc t rea 30h dout 0 31h col add 2 row add 1 row add 2 row add 3 00h t rcbsy col add 1 t rhw dout 1 t clh t ch t ds t wb t cls t cs dout 31h 1 we# ce# ale cle re# r/b# i/ox column address 0 page address m t rc t rea dout 0 t rhw dout 1 dont care column address 0 t clh t ch t rea t cea t rhw t ds t rr t rcbsy t wb column address 0 dout 0 dout 3fh dout 0 dout t cls t cs t rc dout 31h t rcbsy dout 1 dout 1 page address m + 1 page address m + 2 1 t dh t dh
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 133 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 96: read page cache random t wc we# ce# ale cle re# r/b# i/ox page address m column address 00h t ds t clh t cls t cs t ch t dh t wb t r 30h 00h col add 2 row add 1 row add 2 row add 3 00h col add 1 page address n column address 00h col add 2 row add 1 row add 2 col add 1 1 we# ce# ale cle re# r/b# i/ox dont care column address 0 t ch t rea t cea t rhw t ds t dh t rr t rcbsy t wb column address 0 dout 0 dout 3fh dout 0 dout t cs t rc 31h t rcbsy dout 1 dout 1 page address m page address n page address n column address 00h col add 2 row add 1 row add 2 row add 3 col add 1 1 t clh t cls
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 134 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 97: read id operation figure 98: program page operation we# ce# ale cle re# i/ox (dqx) address, 1 cycle 90h 00h or 20h byte 2 byte 0 1 byte 1 byte 3 byte 4 t ar t rea t whr we# ce# ale cle re# rdy i/ox (dqx) t wc t adl 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t whr t wb dont care
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 135 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 99: program page operation with ce# ?don?t care? figure 100: program page operation with change write column address (5 cycles) data input 10h we# ce# t wp t ch t cs dont care data input 80h cle ce# we# ale i/ox (dqx) we# ce# ale cle re# rdy i/ox (dqx) t wc serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in m d in n t adl t ccs change write column command column address read status command serial input 85h t prog t wb t whr dont care col add 1 col add 2 d in p d in q 70h status 10h
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 136 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 101: program page cache figure 102: program page cache ending on 15h we# ce# ale cle re# rdy i/ox (dqx) 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial input t wc dont care 80h t adl row add 3 we# ce# ale cle re# i/ox (dqx) 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page C 1 serial input t wc dont care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page C 1 program successful t adl t whr t whr t adl
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 137 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory timing diagrams micron confidential and proprietary advance figure 103: copyback figure 104: erase block operation we# ce# ale cle re# rdy i/ox (dqx) t wb t prog t wb busy busy read status command t wc dont care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h col add 2 row add 1 row add 2 row add 3 35h (or 30h) col add 1 85h data 1 t r data input optional we# ce# ale cle re# rdy i/ox (dqx) read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr dont care i/o0 = 0, pass i/o0 = 1, fail
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 138 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory package dimensions micron confidential and proprietary advance package dimensions figure 105: 48-pin tsop type 1 cpl (wp package code) notes: 1. all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 139 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory package dimensions micron confidential and proprietary advance figure 106: 48-pin tsop type 1 ocpl (wc package code) notes: 1. all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 12.00 0.08 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 for reference only 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 140 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory package dimensions micron confidential and proprietary advance figure 107: 52-pad ulga package notes: 1. all dimensions are in millimeters. 2. solder pads are nonsol der-mask defined (nsmd). 3. primary datum a (seating plane) is defined by the bottom term inal surface. metallized test terminal lands or interconnect terminals need not extend below th e package bottom sur - face. pad a1 id seating plane 0.10 a a 0.65 max pad a6 3.00 4.00 2.00 2.00 typ 6.00 12.00 0.10 10.00 5.00 2.00 typ 6.00 0.05 40x ?0.70 0.05 pads ? 0.70 non solder mask defined. 1 12x ?1.00 0.05 pads ? 1.00 non solder mask defined. 1 mold compound: epoxy novolac substrate material: plastic laminate 13.00 12.00 10.00 5.00 6.00 2.00 typ 8.50 0.05 6.50 7.80 17.00 0.10 c l c l ?0.70 pad a1 id pad a1 note 1: pads are plated with 5-16 microns of nickel followed by a minimum of 0.50 microns of soft wire bondable gold (99.9% pure).
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 141 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory package dimensions micron confidential and proprietary advance figure 108: 100-ball vbga (package code h1), 1218 notes: 1. all dimensions in millimeters . ball a1 id solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu) mold compound: epoxy novolac substrate material: plastic laminate ball a1 id 0.1 a a 0.64 0.05 100x ?0.45 dimensions apply to solder balls post-reflow. pre-reflow balls are ?0.42 on ?0.4 smd ball pads. 16 5 8 7 9 0.05 18 0.1 1 typ 1 typ 1 typ 9 4.5 6 0.05 12 0.1 1.0 max seating plane 10987654 321 a b d e f g h j k l m n p t u exposed plated features in all corners are floating nonbiased metal.
draft 2/ 27/ 2009 pdf: 09005aef8386131b / source: 09005aef838cad98 micron technology, inc., reserves the right to change products or specifications without notice. m61a_async_sync_nand.fm - rev. a 2/09 en 142 ?2008 micron technology, inc. all rights reserved. 8gb asychronous/synchronous nand flash memory revision history micron confidential and proprietary advance revision history rev a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/09 ?initial release ?

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